VOLUME 9 – NÚMERO 1 – ANO 2009

Microelectronics Students Forum 2009

August 31th to September 3th, 2009
Natal, RN - Brazil

CORPO EDITORIAL

Ivan Saraiva – UFRN
Coordenador geral do evento

Salvador Gimenez – FEI
Coordenador de Programa

Manoel Eusébio de Lima – UFPE
Coordenador de Programa

ARTIGOS

FIRST AND SECOND ORDER SUBSTRATE BIAS INFLUENCE ON FINFETS
Rudolf Bühler, Paula Agopian, Renato Giacomini, FEI, Brazil; João Martino, Univesity of São Paulo, Brazil

IMPACT OF THE HALO REGION ON FLOATING BODY EFFECTS IN TRIPLE GATE FINFETS
Milene Galeti, Michele Rodrigues, João Antonio Martino, Eddy Simoen, University of São Paulo, Brazil; C Claeys, IMEC, Belgium

EVALUATION OF THE DRAIN LEAKAGE CURRENT BEHAVIOR IN DOUBLE GATE FINFETS
Jorge Giroldo Jr., Marcello Bellodi, FEI, Brazil

CROSS-SECTION SHAPE INFLUENCE ON SURROUNDING MUGFETS
Marcelo Sandri, Márcio Martino, Paula Agopian, João Martino, University of São Paulo, Brazil

MULTIPLES THRESHOLD VOLTAGES IN TRAPEZOIDAL CHANNEL MUGFETS
Maria Glória Caño de Andrade, João Antonio Martino, University of São Paulo, Brazil

THE CORNER EFFECT INFLUENCE ON DRAIN CURRENT IN LOW-DOPPED ROUNDED CORNERS TRIPLE-GATE DEVICES
Rodrigo Bechelli, Renato Giacomini, FEI, Brazil

SYSTEM TEST OF ELECTRON MULTIPLYING CCD CHARACTERIZATION
Julián David Rodríguez Ramirez, EPUSP, Brazil; Dani Guzman, Durham University, UK; Claudia Mendes de Oliveira, University of São Paulo, Brazil; Francisco Javier Ramirez Fernandez, EPUSP, Brazil

TWO-DIMENSIONAL NUMERIC MODELING OF PLASMA ETCHING
Regina Peixoto, Edval Santos, Federal University of Pernambuco, Brazil

CONTROL ACCESS SYSTEM USING RFID TECHNOLOGY
Wagner Régis, Michael Taynnan, Daniella Dias, Israel Portela, Jeosafá Júnior, Federal Institute of Education, Science and Technology of Paraiba, Brazil

ON THE ELMORE "FIDELITY" UNDER NANOSCALE TECHNOLOGIES
Tiago José Reimann, Glauco Borges Valim dos Santos, Ricardo Augusto da Luz Reis, Federal University of Rio Grande do Sul, Brazil

IMPLEMENTATION OF RSA CRYPTOSYSTEM IMMUNE TO TIMING ATTACKS
Ítalo Sampaio, Jamile Martins, Mila Maracaba, Jardel Silveira, Helano Castro, Federal University of Ceara, Brazil

FPGA DESIGN OF A MLP ARTIFICIAL NEURAL NETWORK ARCHITECTURE
Antonyus Ferreira, Edna Barros, Teresa Ludermir, Federal University of Pernambuco, Brazil

FPGA PROTOTYPING OF AN USB HOST CONTROLLER
Hudson Veloso, Diego Melo, Renata Garcia, Marcelo Lucena, Antonyus Pyetro, Edna Barros, Federal University of Pernambuco, Brazil

A FPGA FFT CORE IMPLEMENTATION
Arthur Rolim, Manoel Lima, Federal University of Pernambuco, Brazil

FUNCTIONAL VERIFICATION OF A USB HOST CONTROLLER
Renata Garcia Oliveira, Edna Natividade da Silva Barros, Federal University of Pernambuco, Brazil

ASPECTS OF IMPLEMENTATION OF AN EDUCATIONAL PLATFORM FOR ROBOT BASED FPGA
Felipe Gurgel, Marcel Siqueira, Marcos Vallim, Federal Technological University of Paraná, Brazil

TOWARDS ACCELERATING LOW-LEVEL VISION IN ROBOTICS
Gianna Araújo, Júlio Melo, José Oliveira, Luiz Gonçalves, Federal University of Rio Grande do Norte, Brazil

AN ADDRESS DECODER FOR VARIABILITY CHARACTERIZATION FOR 65NM MOS TRANSISTORS
Felipe Correa Werle, Giovano da Rosa Camaratta, Juan Pablo, Sergio Bampi, Federal University of Rio Grande do Sul, Brazil

LAYOUT DESIGN OF CMOS INVERTERS WITH CIRCULAR AND CONVENTIONAL GATE MOSFETS BY USING IC STATION OF MENTOR
Klaus Cirne, Salvador Gimenez, FEI, Brazil

IMPLEMENTING DIAMOND SOI MOSFET LAYOUT
Raffaello Claser, Salvador Pinillos Gimenez, FEI, Brazil

MAPPING AND UNDERSTANDING THE MULTIVARIATE AND MULTI-OBJECTIVE OPTIMIZATION BEHAVIOUR OF A SOI CMOS OTA USING GENETIC ALGORITHMS
Thiago Turcato do Rego, Salvador Gimenez, Carlos Thomaz, FEI, Brazil

PLANAR TRANSISTOR NETWORK VISUALIZATION ALGORITHM
Rafael Hansen da Silva, Vinicius Callegaro, André Inácio Reis, Renato Perez Ribas, Federal University of Rio Grande do Sul, Brazil

A PHASE AND FREQUENCY DETECTOR AND CHARGE PUMP FOR LOCAL OSCILLATOR IN A ZIGBEE TRANSCEIVER
Guilherme Freitas, Sergio Bampi, Federal University of Rio Grande do Sul, Brazil

DESIGN AND CHARACTERIZATION OF A 900MHZ LC VOLTAGE CONTROLLED CMOS OSCILLATOR
Heider Marconi Guedes Madureira, José Edil Guimarães de Medeiros, José Camargo da Costa, University of Brasília, Brazil

A NEW LOW POWER EXPLORATION MECHANISM BASED ON DESIGN OF EXPERIMENTS (DOE) AND TWO-LEVEL HIERARCHIES
Filipe Cordeiro, Abel Silva-Filho, Federal University of Pernambuco, Brazil

DESIGN OF AN ANALOG-TO-DIGITAL CONVERTER
Leandro Mota, Antonio Wallace, João Dantas, Fernando Sousa, Federal University of Rio Grande do Norte, Brazil

IMPACT OF DIFFERENT OP-AMPS IN CMOS BANDGAP REFERENCES IMPLEMENTED IN 0.18µM TECHNOLOGY
Dalton Colombo, Gilson Wirth, Federal University of Rio Grande do Sul, Brazil

WIRELESS TEMPERATURE SENSING USING ZIGBEE NETWORKS
Marcelo Besch, Walter Gadelha, Fernando de Sousa, Federal University of Rio Grande do Norte, Brazil

AN UDP/IP NETWORK STACK IN FPGA
Fernando Luís Herrmann, Guilherme Perin, Josué Paulo José de Freitas, Rafael Bertagnolli, João Baptista dos Santos Martins, Federal University of Santa Maria, Brazil

REDUCING SOC DESIGN EFFORT BY ABSTRACTING COMMUNICATION DETAILS USING A ESL CENTRIC SERVICE BASED UML PROFILE
Millena Gomes, Cristiano Araújo, Adriano Sarmento, Ciro Ceissler, Josiane Bezerra, Denys Farias, Federal University of Pernambuco, Brazil

A FPGA-BASED NETWORK STACK WITH A REDUCED NUMBER OF LAYERS
Josue P. J. de Freitas, Gustavo Dessbesell, Joao Baptista dos Santos Martins, Federal University of Santa Maria, Brazil

NETWORK-ON-CHIP PERFORMANCE EVALUATION ON FPGA: A HARDWARE/SOFTWARE CORE-BASED SOLUTION
Miklécio Costa, Ivan Saraiva Silva, Federal University of Rio Grande do Norte, Brazil

ANALYSIS OF POWER CONSUMPTION USING A NEW METHODOLOGY FOR THE CAPACITANCE MODELING OF COMPLEX LOGIC GATES WITH DOGBONE TRANSISTOR
Sidinei Ghissoni, Ricardo Reis, Federal University of Rio Grande do Sul, Brazil

EVALUATION OF STANDARD CELL LIBRARIES WITH DIFFERENT TEMPLATES AND GATE DESIGN APPROACHES
Diogo da Silva, Paulo Butzen, André Reis, Renato Ribas, Federal University of Rio Grande do Sul, Brazil

EFFECT OF COMPLEX CELL FUNCTIONS IN THE TECHNOLOGY MAPPING PROCESS
Pedro Egidio Menegaz Paganela, André I. Reis, Renato P. Ribas, Federal University of Rio Grande do Sul, Brazil

A KERNEL-BASED APPROACH FOR FACTORING LOGIC FUNCTIONS
Vinicius Callegaro, Federal University of Rio Grande do Sul, Brazil; Leomar S. da Rosa, Federal University of Pelotas; André I. Reis, Renato P. Ribas, Federal University of Rio Grande do Sul, Brazil

CMOS A/D FLASH CONVERTER BASED ON THE QUANTIZATION OF THE THRESHOLD VOLTAGE
André Dantas Ferreira, Edval J. P. Santos, Federal University of Pernambuco, Brazil

AN OPTIMIZATION-BASED TOOL FOR CIRCUIT LEVEL SYNTHESIS ANALOG INTEGRATED CIRCUITS
Lucas Compassi Severo, Alessandro Girardi, Federal University of Pampa, Brazil

VHDL-AMS MODELING OF ANALOG/MIXED-SIGNAL IP BLOCKS
João Vitor Bernardo Pimentel, José Camargo da Costa, University of Brasília, Brazil

MEASUREMENT RESULTS OF THE UFRN DIDACTIC CHIP
Francisco Marcelino Brito Júnior, Fernando Rangel de Sousa, Federal University of Rio Grande do Norte, Brazil

2-INPUT NEUROMORPHIC AND LOGIC GATE BASED ON INTEGRATE-AND-FIRE NEURON USING CMOS TECHNOLOGY
Leonardo Enzo Brito da Silva, Fernando Rangel de Sousa, Federal University of Rio Grande do Norte, Brazil

DEVELOPING A MULTICHANNEL HIGH SPEED DDR SDRAM MEMORY CONTROLLER: A CASE STUDY FOR H.264/AVC DECODER
Alexsandro Cristovão Bonatto, Andre Borin Soares, Altamiro Amadeu Susin, Federal University of Rio Grande do Sul, Brazil

AN H.264/AVC DECODER FRONTEND TARGETING BROADCASTING DTV FOR SBTVD
Márlon Allan Lorencetti, Letícia Vieira Guimarães, Altamiro Amadeu Susin, Federal University of Rio Grande do Sul, Brazil

A NETWORK-ON-CHIP BASED ARCHITECTURE FOR H.264 MOTION ESTIMATION
Alba Sandyra Bezerra Lopes, Ivan Saraiva Silva, Federal University of Rio Grande do Norte, Brazil

THE IMPORTANCE OF ESTABLISHING A METHODOLOGY FOR ANALYSIS OF AN ALGORITHM BETWEEN ARCHITECTURES
Bruno Silva, Manoel Lima, Veronica Teichrieb, Queliane Carvalho, Federal University of Pernambuco, Brazil

CABARE: AN EDUCATIONAL RECONFIGURABLE GENERAL PURPOSE PROCESSOR
Tadeu Ferreira Oliveira, Ivan Saraiva Silva, Federal University of Rio Grande do Norte, Brazil

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