Monday, September 8, 2003

Tutorial Day

7:30 to 18:00

Registration

8:30

to

10:30

SystemC: From Language to Applications,

From Tools to Methodologies

Grant Martin, Cadence Bekeley Labs, USA

Abstract:
This tutorial will cover SystemC from more than just a language perspective. It will start with a brief survey of language features and capabilities, including some of the more recent developments such as the SystemC Verification Library.     The usage of several of these language features, in particular for system-level modelling, design, verification and refinement will be illustrated.    We will then address many interesting applications of SystemC drawn from a number of different industrial and academic research groups. Next, we will talk about current tools available for design modelling, analysis and implementation with SystemC, covering the areas of cosimulation, synthesis, analysis, refinement, and testbenches, illustrating them with examples. Of course, tools are not enough; we will cover a number of methodology examples, in particular illustrating the use of SystemC in building complete design flows for complex SoC and system designs. This will also illustrate the linkage between SystemC and other design languages. We will close with a few notes on possible future SystemC evolutions.

10:30 to 11:00

Break

11:00

to

13:00

System-Level Design for FPGAs

Patrick Lysaght, Xilinx , USA

Abstract:
The complexity of FPGAs has progressed to the point where they are likely to become the dominant platform for the majority of system on chip (SoC) design starts within the foreseeable future. Many of the system-level challenges that we were first encountered with ASIC SoCs are fast becoming relevant for high end FPGAs. Functional verification and debug in particular are emerging as two of the biggest concerns. In this talk we review the traditional and emerging approaches to system-level design used with ASIC designs and evaluate their appropriateness in the context of FPGAs. We proceed to explore how FPGA technology might present new opportunities to offset the system-level design challenges. Finally, we look at some novel approaches to the problem that exploit the unique features of FPGAs.

13:00 to 14:30

Lunch

14:30

to

16:30

High Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: the coming of age for RF/digital mixed-signal system-on-a-package

Luiz M Franca-Neto, Intel R&D Labs, USA

Abstract:
This tutorial will present recent developments in CMOS device and circuit technology, which enable the disruptive ascent of CMOS logic technology to the forefront of high performance RF/microwave communication circuit and system designs fully integrated with high performance digital processors on the same die. Device level characteristics of CMOS and bipolar are compared vis-à-vis, and their meaning to circuit design and system performance are analyzed. Circuit level solutions to compensate for intrinsic drawbacks on logic CMOS technology are introduced and their adequacy to RF/microwave wireless integrated system stressed. New CMOS-compatible structures, already available as deep Nwell implants, are shown to be the only required device level addition to advanced CMOS processes to enable mixed-signal integration. Integration of delicate RF receivers (-76dBm sensitivity)  with as noisy a digital processors as a Pentium 4 (1GHz, 55Watts, 104million transistors) is thus shown to be possible by exploitation of substrate noise spectrum structure and proper receiver design. RF/microwave ISM (Industrial Scientific and Medical) bands allocated by the FCC in the US at 2.4GHZ, 5.2GHz, 17GHz and 24GHz are the targeted bands for Wireless LAN solutions with CMOS. These bands can also be the merging field for both data and voice (cell phone) communications. CMOS circuits for all these bands, as well as the differences between digital and analog/RF design methods are presented. The tutorial concludes with a prelude of what is ahead and where very promising research and product developments are likely to come from.

16:30 to 16:45

Break

16:45

to

18:25

Business Sessions

Tuesday, September 9, 2003

8:00 to 18:00

Registration

8:20

to

10:00

1A: Advanced Amplifier Design

Moderator:  Carlos A. dos Reis Filho, UNICAMP, Brazil

1.     Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35um
J. A. P. Azevedo, T. C. Pimenta – UNIFEI, Itajuba, Brazil

2.     A Methodology for CMOS Low Noise Amplifier Design
E. F. Roa Fuentes, J. Navarro Soares, W. van Noije – LSI, USP, Brazil

3.     Design of a Reusable Rail-to-Rail Operational Amplifier
P.  Aguirre, F. Silveira – Univ. de la Republica, Uruguay

4.     Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs
S.P. Gimenez, M. A. Pavanello, J. A. Martino – LSI, USP, Brazil
S. Adriaensen, D. Flandre – Univ. Catholique de Louvain, Belgium

1B: Logic Synthesis Techniques

Moderator:  Ney Calazans, PUC-RS, Brazil

1.     Boolean Technology Mapping based on Logic Decomposition
M. Damiani – Sierra Design Automaion, CA, USA
A. Shlyakhtenko – DariaSoft, CA, USA

2.     Retiming Finite State Machines to Control Hardened Data-Paths
I. Augé, F. Donnet, F. Pétrot – Univ. Pierre et Marie Curie, LIP6, Paris, France

3.     Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
L. P. Carloni, A. L. Sangiovanni-Vincentelli – U.C. Berkeley, CA, USA

4.     Simplification of Toffoli Networks via Templates
D. Maslov, G. W. Dueck – Univ. of New Brunswick, Canada
D. M. Miller – Univ. of Victoria, Canada

10:00 to 10:20

Break

10:20

to

11:10

2: Invited Talk

SystemC and the future of Design Languages: Opportunities for Users and Research

Grant Martin, Cadence Berkeley Labs, USA

Moderator: Flavio Wagner, UFRGS, Brazil

11:10

to

12:00

3A: Digital Design Techniques

Moderator:  José Güntzel, UFPel, Brazil

1.     A New Pipelined Array Architecture for Signed Multiplication
E. da Costa – UCPel, Pelotas, Brazil,
S. Bampi – UFRGS, Brazil,
J. Monteiro – IST/INESC, Lisboa, Portugal

2.     Novel Design Mehodology for High-Performance XOR-XNOR Circuit Design
S. Goel, M. A. Elgamel, M. A. Bayoumi – Univ. of Louisiana at Lafayette, USA

 3B: High-Level and Co-Design Approaches

Moderator:  Juergen Becker, Univ. of Karlsruhe, Germany

1.     Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures
A. Rettberg, F. Dittmann, M. Zanella, T. Lehmann – Univ. of Paderborn, Germany

2.     DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware / Software Architectures
M. P. Véstias, H. C. Neto –
INESC-ID/IST, Lisboa, Portugal

12:00 to 14:00

Lunch

14:00

to

14:30

Chip in Sampa

Opening Session

Wilhelmus Van Noije (Chip in Sampa General Chair)
Roberto Jaguaribe (MDIC)
Arthur Pereira Nunes (MCT)
Anderson Jorge de Souza Filho (ABINEE)
Ivan Falleiros (USP)
Vanda Scartezzini (SCTDE/SP)

14:40

to

15:30

Keynote Speech

New Technologies: Impacts and Implementations

Kevin Knox, AMD , USA

15:30

to

16:20

Keynote Speech 2

Title: Coming Challenges in Microprocessors

Speaker: Shih-Lien Lu, Intel Corporation, USA

16:20 to 16:40

Break

16:40

to

18:00

Business Sessions

18:00 to 18:30

Break

18:30

to

20:00

Panel 1 (in Portuguese)

Microeletrônica - Cenários para a reinserção da Indústria de Chips no Brasil

    Moderator: Sergio Bampi, UFRGS, Brazil

    Panelists: Francelino L. Grando (MCT)

                    Regina M. V. Gutierrez (BNDES)

                    Wanderley Marzano (Aegis Ltda.)

                    Toshihiko Komatsu (ABINEE)

                    Armando Gomes (Motorola)

                    Nery Santos Filho (CEITEC)

                    Arnaldo Serrão (MDIC)

Wednesday, September 10, 2003

8:20

to

10:00

4A: Mapping Applications onto FPGAs

Moderator:  Renato Ribas, UFRGS, Brazil

1.     ME64 – A Highly Scalable Parallel Architecture for Motion Estimation in FPGA
D. Zandonai, S. Bampi – UFRGS, Brazil,
M. Bergerman – Genius Inst. of Technology, Manaus, Brazil

2.     Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm
A. G. S. Filho, A. C. Frery, C. C. de Araujo, H. Alice, J. Cerqueira, J. A. Loureiro, M. E. de Lima, M. S. Oliveira, M. M. Horta – UFPE, Pernambuco, Brazil

3.     Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs
S. Ferreira, F. Haffner, L. F. Pereira, F. Moraes – PUC-RS, Brazil

4.     FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic
N. Nedjah, L. de Macedo Mourelle – UERJ, Rio de Janeiro, Brazil

4B: IP Integration Techniques

Moderator:  Grant Martin, Cadence, USA

1.     An XML Format based Integration Infrastructure for IP based Design
M. Visarius, J. Lessmann, W. Hardt – Univ. of Paderborn, Germany,
F. Kelso – Univ. of Minnesota, USA
W. Thronicke – Siemens, Germany

2.     Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-simulation Environment
U. R. F. Souza, J. K. Sperb, B. A. Mello, F. R. Wagner – UFRGS, Brazil

3.     A Fast IP-Core Integration Methodology for SoC Design
J. A. de Oliveira Filho, M. E. de Lima, P. R. Maciel, J. Moura, B. Celso – UFPE, Pernambuco, Brazil

4.     A Universal High-Performance Analog Interface for Signal Processing SOCs
E. E. Fabris, L. Carro, S. Bampi – UFRGS, Brazil

10:00 to 10:20

Break

10:20

to

11:10

5: Invited Talk

Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems

Santanu Dutta, Philips Semiconductors, USA

Moderator: Guido Araújo, UNICAMP, Brazil

11:10  to 12:00

6A: Asynchronous Design Techniques

Moderator:  TBD

1.     Automatic Generation of 1-of-M QDI Asynchronous Adders
J. L. Fragoso, G. Sicard, M. Renaudin – TIMA, Grenoble, Rance

2.     Exclusion Relation of k Out Of n and the Synthesis of Speed-Independent Circuits
A. Pereira, A. R. Borges, A. Ferrari – Univ. de Aveiro, Portugal

6B: Networks-on-Chip

Moderator:  Flavio Wagner, UFRGS, Brazil

1.     Algorithms and Tools for Network on Chip Based System Design
T. Lei, S. Kumar, Jönköping Univ. Sweden

2.     SoCIN: A Parametric and Scalable Network-on-Chip
C. A. Zeferino, A. A. Susin – UFRGS, Brazil

12:00 to 14:00

Lunch

14:00

to

15:40

7A: Application Specific RF and Analog Design

Moderator:  Luiz Franca-Neto, Intel, USA

1.     A Low Ripple Fully Integrated Charge Pump Regulator
J. Soldera, A. Vilas Boas, A. Olmos – Motorola, Jaguariúna, Brazil

2.     A Temperature Compensated Fully Trimmable On-Chip IC Oscillator
A. Olmos – Motorola, Jaguariúna, Brazil

3.     Bias Dependence of Noise Correlation in MAGFETs
F. C. Castaldo – UEL, Londrina, Brazil,
J. P. Cajueiro, C. A. dos Reis Filho – UNICAMP, Brazil

4.     A Charge Correction Cell for FGMOS-based Circuits
E. O. Rodríguez-Villegas, A. Yúfera, A. Rueda – IMSE-CNM, Univ. de Sevilla, Spain

7B: Applications of Formal Methods to Design

Moderator:  Ricardo Jacobi, Univ. de Brasilia, Brazil

1.     Unified Theory to Build Cell-Level Transistor Networks from BDDs
R. E. B. Poli, F. R. Schneider, R. P. Ribas, A. I. Reis – UFRGS, Brazil

2.     Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
M. Ayala-Rincon, R. B. Nogueira, C. H. Llanos, R. P. Jacobi – Univ. de Brasília, Brazil,
R. W. Hartenstein – Univ. Kaiserslautern, Germany

3.     Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification
G. Logothetis, C. Metzler – Univ. of Karlsruhe, Germany
K. Schneider – Univ. of Kaiserslautern, Germany

4.     A Consumer Report on BDD Packages
G. Janssen, IBM T. J. Watson Research Center, NY, USA

15:40 to 16:00

Break

16:00

to

17:30

Panel 2 (in English)

Future Systems Design: The Convergence of Technology, Design and Tools

    Moderator: Wolfgang Rosenstiel

    Panelists: Cor Claeys, IMEC, Belgium

                    Santanu Dutta, Philips Semiconductors, USA

                    Patrick Lysaght, Xilinx , USA

                    Grant Martin, Cadence Berkeley Labs, USA

Thursday, September 11, 2003

8:20

to

10:00

8A: Novel Architectures

Moderator:  Sergio Bampi, UFRGS, Brazil

1.     A New Hybrid Parallel/Reconfigurable Architecture: the X4CP32
A. Azevedo, R. Soares, I. Saraiva Silva – UFRGN, Rio Grande do Norte, Brazil

2.     Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture
A. Rettberg, M. Zanella, T. Lehmann, U. Dierkes, C. Rustemeier – Univ. of Paderbon, Germany

3.     Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration
J. Becker, A. Thomas, M. Scheer – Univ. of Karlsruhe, Germany

4.     Situated Learning on FPGA for Superscalar Microprocessor Design Education
R. Takahashi – Hiroshima City Univ. Japan,
H. Ohiwa – Keio Univ., Japan

8B: Noise Analysis and Layout

Moderator:  Luigi Carro, UFRGS, Brazil

1.     On-chip Decoupling Capacitor Optimization for Noise and Leakage Reduction
H. H. Chen, S. Neely, M. F. Wang, G. Co – IBM T. J. Watson Research Center, NY, USA

2.     Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction
M. A. Elgamel, M. A. Bayoumi – Univ. of Louisiana at Lafayette, USA

3.     A New Continuous Switching Window Computation with Crosstalk Noise
J. M. Wang, O. Hafiz – Univ. of Arizona at Tucson, USA
P. Chen – Cadence, USA

4.     Improving Simulated Annealing Placement by applying Random and Greedy Mixed Perturbations
R. F. Hentschke, R. Reis – UFRGS, Brazil

10:00 to 10:20

Break

10:20

to

11:10

9: Invited Talk

Future Design Tools for Platform FPGAs

Patrick Lysaght, Xilinx , USA

Moderator: Wolfgang Rosenstiel, Tübingen University , Germany

11:10  to 12:00

10A: Issues in Reconfigurable Architectures

Moderator:  Fernando Moraes, PUC-RS, Brazil

1.     Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-offs and Limitations
J. Becker, M. Huebner, M. Ullmann – Univ. of Karlsruhe, Germany

2.     Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs
R. L. Zuim, C. J. N. Coelho Jr., L. F. Moreira, A. O. Fernandes, J. M. da Mata, D. C. da Silva Jr. – UFMG, Brazil

10B: Timing Analysis and Layout

Moderator:  Geert Janssen, IBM, USA

1.     Improving Critical Path Identification in Functional Timing Analysis
D. Ferrão, G. Wilke, R. Reis – UFRGS, Brazil,
J. L. Güntzel – UFPel, Pelotas, Brazil

2.     A Transistor Sizing Method Applied to an Automatic Layout Generation Tool
C. Santos, G. Wilke, C. Lazzari, R. Reis – UFRGS, Brazil,
J. L. Güntzel – UFPel, Pelotas, Brazil

12:00 to 14:00

Lunch

14:00

to

15:40

11A: Innovative Approaches to RF and Analog Design Problems

Moderator:  Fernando Castaldo, UEL, Brazil

1.     Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35um Technology
A. Girardi, F. P. Cortes, E. Fabris, S. Bampi – UFRGS, Brazil

2.     Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages
A. J. Ginés, E. J. Peralías, A. Rueda – IMSE-CNM, Univ. de Sevilla, Spain

3.     Design Methodologies for High-speed CMOS Photoreceiver Front-ends
F. Tissafi-Drissi, I. O'Connor, F. Mieyeville, F. Gaffiot – E.C. de Lyon, France

4.     Testing RF Signal Paths Using Spectral Analysis and Subsampling
M. Negreiros, E. Schuler, L. Carro, A. A. Susin – UFRGS, Brazil

11B: High-Level Validation and Modeling

Moderator:  Marcelo Lubaszewski, UFRGS, Brazil

1.     Accurate Dependability Analysis of CAN-based Networked Systems
J. Pérez – Univ. de la Republica, Uruguay,
M. S. Reorda, M. Violante – Politecnico di Torino, Italy

2.     ReCoNet: Modeling and Implemention of Fault Tolerant Distributed Reconfigurable Hardware
C. Haubelt, D. Koch, J. Teich – Univ. of Erlangen-Nuremberg, Germany

3.     CACO-PS: A General Purpose Cycle-accurate Configurable Power Simulator
A. C. S. Beck Filho, J. C. B. Mattos, F. R. Wagner, L. Carro – UFRGS, Brazil

4.     From VHDL Register Transfer Level to SystemC Transaction Level Modeling: a Comparative Case Study
N. Calazans, E. Moreno, F. Hessel, V. Rosa, F. Moraes, E. Carara – PUC-RS, Brazil

15:40 to 16:00

Break

16:00

to

17:30

Panel 3 (in Portuguese)

Como alavancar a pesquisa e desenvolvimento em Microeletrônica no Brasil?

    Moderator: Wilhelmus van Noije, USP, Brazil

    Panelists:  Reinaldo Bergamaschi, IBM Research , USA

                    Carlos H. de Brito Cruz, UNICAMP, Brazil

                    José R. Leite, CNPq , Brazil

                    Sergio M. Rezende, FINEP, Brazil

                    Flavio R. Wagner, UFRGS / SBC, Brazil