year we have already confirmed the prominent speakers:
- Grant Martin
- Cadence, USA
SystemC: From Language to Applications, From Tools to Methodologies
- Patrick Lysaght
- Xilinx, USA
System-Level Design for FPGAs
- Luiz M. Franca-Neto
- Intel R&D Labs, USA
High Performance RF/Microwave Integrated Circuits in Advanced Logic
CMOS Technology: the coming of age for RF/digital mixed-signal system-on-a-package
From Language to Applications, From Tools to Methodologies
Martin - Cadence, USA.
tutorial will cover SystemC from more than just a language perspective.
It will start with a brief survey of language features and capabilities,
including some of the more recent developments such as the SystemC Verification
Library. The usage of several of these language features, in particular
for system-level modelling, design, verification and refinement will be
illustrated. We will then address many interesting applications of SystemC
drawn from a number of different industrial and academic research groups.
we will talk about current tools available for design modeling, analysis
and implementation with SystemC, covering the areas of co-simulation,
synthesis, analysis, refinement, and testbenches, illustrating them with
examples. Of course, tools are not enough; we will cover a number of methodology
examples, in particular illustrating the use of SystemC in building complete
design flows for complex SoC and system designs. This will also illustrate
the linkage between SystemC and other design languages. We will close
with a few notes on possible future SystemC evolutions.
Martin is a Fellow in the Labs of Cadence Design Systems. He joined Cadence
in late 1994. Before that, Grant worked for Burroughs in Scotland for
6 years and Nortel/BNR in Canada for 10 years. He received his Bachelor's
and Master's degrees in Mathematics (Combinatorics and Optimisation) from
the University of Waterloo, Canada, in 1977 and 1978.
is a co-author of the books Surviving the SOC Revolution: A Guide to Platform-Based
Design, 1999, and System Design with SystemC, 2002, and a co-editor of
the books Winning the SoC Revolution: Experiences in Real Design, and
UML for Real: Design of Embedded Real-Time Systems, June 2003, all published
by Kluwer Academic Publishers. He co-chaired the VSI Alliance Embedded
Systems study group in the summer of 2001. His particular areas of interest
include system-level design, System-on-Chip, Platform-Based design, and
Design for FPGAs
Patrick Lysaght - Xilinx, USA.
of FPGAs has progressed to the point where they are likely to become the
dominant platform for the majority of system on chip (SoC) design starts
within the foreseeable future. Many of the system-level challenges that
we were first encountered with ASIC SoCs are fast becoming relevant for
high end FPGAs. Functional verification and debug in particular are emerging
as two of the biggest concerns. In this talk we review the traditional
and emerging approaches to system-level design used with ASIC designs
and evaluate their appropriateness in the context of FPGAs. We proceed
to explore how FPGA technology might present new opportunities to offset
the system-level design challenges. Finally, we look at some novel approaches
to the problem that exploit the unique features of FPGAs.
Lysaght is Senior Director, Xilinx Research Labs, San Jose since 2001.
He joined the senior management team of Xilinx Research Labs with the
charter to create a thriving research organization within Xilinx Inc.
Author of more than 40 technical papers and reports.
Lecturer, Electronic and Electrical Engineering and Institute for System
Level Integration, April 1998 - Sept. 2001: Established an international
reputation for innovative, original research that was well supported and
Electronic and Electrical Engineering, University of Strathclyde, Jan.
1990 - Mar. 1998: Founded and nurtured a new research group, earned a
reputation for excellence in teaching and consulted widely with industry
and launched Europe's first research programme dedicated to investigating
dynamically reconfigurable logic. Designed the world's first computer
aided design tools for specifying and functionally simulating dynamically
reconfigurable logic and reported several novel applications of the technology.
Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology:
the coming of age for RF/digital mixed-signal system-on-a-package
Luiz M. Franca-Neto - Intel R&D Labs, USA.
tutorial will present recent developments in CMOS device and circuit technology,
which enable the disruptive ascent of CMOS logic technology to the forefront
of high performance RF/microwave communication circuit and system designs
fully integrated with high performance digital processors on the same
die. Device level characteristics of CMOS and bipolar are compared vis-à-vis,
and their meaning to circuit design and system performance are analyzed.
Circuit level solutions to compensate for intrinsic drawbacks on logic
CMOS technology are introduced and their adequacy to RF/microwave wireless
integrated system stressed. New CMOS-compatible structures, already available
as deep Nwell implants, are shown to be the only required device level
addition to advanced CMOS processes to enable mixed-signal integration.
Integration of delicate RF receivers (-76dBm sensitivity) with as noisy
a digital processors as a Pentium 4 (1GHz, 55Watts, 104million transistors)
is thus shown to be possible by exploitation of substrate noise spectrum
structure and proper receiver design. RF/microwave ISM (Industrial Scientific
and Medical) bands allocated by the FCC in the US at 2.4GHZ, 5.2GHz, 17GHz
and 24GHz are the targeted bands for Wireless LAN solutions with CMOS.
These bands can also be the merging field for both data and voice (cell
phone) communications. CMOS circuits for all these bands, as well as the
differences between digital and analog/RF design methods are presented.
The tutorial concludes with a prelude of what is ahead and where very
promising research and product developments are likely to come from.
Franca-Neto earned the Electronic Engineer degree from Instituto Tecnologico
de Aeronautica, ITA, 1989, and the M.Sc. and Ph.D. degrees both in Electrical
Engineering from Stanford University, USA, in 1995 and 1999, respectively.
In his Ph.D. work, he devised and developed a new approach to noise phenomena
in semiconductor devices. This led him to predict and experimentally demonstrate
excess noise in sub-micron field effect transistor can be controlled by
doping profiling along the channel and mechanical stress of the semiconductor
crystal lattice. In USA since 1993, he had appointments with Hewlett-Packard
Laboratories, Palo Alto, California, 1995 and Texas Instruments, Dallas,
Texas, 1996. Since 1999, he is with Intel Corporation, where he is a Staff-Research-Scientist
with Intel Research & Development (former Intel Laboratories). He
is an industrial mentor for two university research projects via SRC (www.src.org)
and is the Intel liaison for another university research (Caltech) via
Intel Research Council. He has 5 issued US patents and 12 pending ones
covering semiconductor devices, circuits and communication systems.