SBMicro 2003
18th SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES
CHIP IN SAMPA

São Paulo, Brazil
September 8-11, 2003

ADVANCE PROGRAM

Monday, September 8, 2003

Tutorial Day

7:30 to 18:00

Registration

8:30

to

10:30

Dielectrics for Submicrometric Devices

Magali Estrada del Cueto, CINVESTAV, Mexico

Abstract:
We present the state of the art of present ultra thin SiO2 and oxynitride layers of less than 3 nm, used as gate dielectrics for MOS devices with submicrometric channel length and their limitations for further channel length reduction. Conduction mechanisms in ultrathin gate dielectrics are analyzed. Other problems present in ultrathin gate dielectrics of less than 2.5 nm for MOS devices are discussed.
The necessity of alternative high dielectric constant gate dielectrics is analyzed, as well as what to look for in them. We review main materials under research and fabrication techniques obtained by different authors. We detail results on room temperature plasma oxidation and photo-CVD techniques developed at our laboratory for single and multilayer gate structures. Advantages and disadvantages of single and multilayer gate structures are also discussed. Presentation also includes a brief look to the problematic of low k dielectrics.

10:30 to 11:00

Break

11:00

to

13:00

Silicon-on-Insulator: Materials and Devices

Jean-Pierre Colinge, University of California, Davis, USA

Abstract:
The first SOI transistors date back to 1964. They were partially depleted devices fabricated on Silicon-on-Sapphire (SOS) substrates. SOS technology was successfully used for numerous military and civilian applications and is still being used to realize commercial HF circuits in fully depleted CMOS. Once the first SOI substrates (the insulator is now silicon dioxide) were available for experimental MOS device fabrication, partially depleted technology the natural choice derived from SOS experience. Partially depleted CMOS continues to be used nowadays and several commercial IC manufacturers have SOI products and product lines such as microprocessors (e.g.: AMD, IBM, Motorola), memory chips (Honeywell).The first fully depleted SOI MOSFET date back to the early 1980's where it was quickly established that these devices exhibited superior transconductance, current drive and subthreshold swing. Fully-depleted SOI technology is being used in commercial products as well (e.g.: OKI, Peregrine).
To improve short-channel characteristics and increase current drive, SOI technology is shifting focus from "classical" single-gate MOSFET architectures to multiple-gate device structures. This tutorial will trace the history of single- and multiple-gate SOI MOSFETs and summarize the electrical characteristics of such devices. The properties of the different types of SOI MOSFETs will be compared and trends will be extrapolated to try to envision future SOI device structures.

13:00 to 14:30

Lunch

14:30

to

16:30

Submicrom Silicon Technologies

Cor Claeys, IMEC, Belgium

Abstract:
The International Technology Roadmap for Semiconductors (ITRS) is predicting the technology evolution for the coming 15 years, required to give the semiconductor industry a competitive market position. This not only implies pushing existing process modules to the limits but also introducing new ones, which most likely will be based on alternative concepts and/or the use of new materials. This presentation will be focusing on a selection of these processing challenges.
First the silicon material requirements will be addressed, including high quality silicon substrates, epitaxial wafers, thin film SOI, SiGe and strained silicon. Subsequently some process modules will be discusses such as e.g. as isolation schemes, gate dielectrics based on high-k materials, silicides and interconnect schemes. Beside the use of novel or alternative materials, attention will also be given to equipment aspects like atomic layer deposition, single wafer processing, flash annealing, etc. The last part will outline the importance of so-called gate engineering, including metal gates, doubles gate structures, vertical replacement gates and FinFETS. These approaches are presently extensive studied and will surely be used for the 45 nm and below emerging silicon technologies.

16:30 to 16:45

Break

16:45

to

18:25

Business Sessions

19:00

to

20:30

SBMicro General Assembly

Tuesday, September 9, 2003

8:00 to 18:00

Registration

8:20

to

10:00

Process Technology - 1

M03: The Effect of Nitrogen Concentration at Silicon Oxynitride Gate Insulators Formed by 28N2+ Implantation into Silicon with Additional Conventional or Rapid Thermal Oxidation
A. G. Felício, J. A. Diniz, J. Godoy Fo., I. Doi, M. A. A. Pudenzi and J. W. Swart

M04: Formation of Nickel Silicides onto (100) Silicon Wafer Surfaces Using a Thin Platinum Interlayer
R. W. Reis, S. G. dos Santos Filho, I. Doi and J. W. Swart

M05: In-Situ and Ion Implantation Nitrogen Doping On Near Stoichiometric a-SiC:H Films
A.R. Oliveira and M.N.P. Carreño

M06: Silicon Carbide Clusters in Silicon Formed by Carbon Ions Implantation
N. A. E. Forhan and I. Pereyra

10:00 to 10:20

Break

10:20

to

12:00

 

SOI - 1

IM01: Multiple-Gate Silicon-On-Insulator MOS Transistor (Invited Paper)
Jean-Pierre Colinge, University of California, Davis, USA

M01: Degradation of Deep Submicron Partially Depleted SOI CMOS Transistors Under MEV Proton or Gamma Irradiation
E. Simoen, J.M. Rafi, A. Mercha, K. De Meyer, C. Claeys, M. Kokkoris, E. Kossionides, G. Fanourakis and A. Mohhamdzadeh

M02: The Leakage Drain Current Behavior in Graded-Channel SOI nMOSFETs Operating up to 300o C
M. Bellodi and J. A. Martino

12:00 to 14:00

Lunch

14:00

to

14:30

Chip in Sampa

Opening Session

Wilhelmus Van Noije (Chip in Sampa General Chair)
Roberto Jaguaribe (MDIC)
Arthur Pereira Nunes (MCT)
Anderson Jorge de Souza Filho (ABINEE)
Ivan Falleiros (USP)
Vanda Scartezzini (SCTDE/SP)

14:40

to

15:30

Keynote Speech

New Technologies: Impacts and Implementations

Kevin Knox, AMD , USA

15:30

to

16:20

Keynote Speech 2

Title: Coming Challenges in Microprocessors

Speaker: Shih-Lien Lu, Intel Corporation, USA

16:20 to 16:40

Break

16:40

to

18:00

Poster Sessions

18:00 to 18:30

Break

18:30

to

20:00

Panel 1 (in Portuguese)

Microeletrônica - Cenários para a reinserção da Indústria de Chips no Brasil

    Moderator: Sergio Bampi, UFRGS, Brazil

    Panelists: Francelino L. Grando (MCT)

                    Regina M. V. Gutierrez (BNDES)

                    Wanderley Marzano (Aegis Ltda.)

                    Toshihiko Komatsu (ABINEE)

                    Armando Gomes (Motorola)

                    Nery Santos Filho (CEITEC)

                    Arnaldo Serrão (MDIC)


Wednesday, September 10, 2003

8:20

to

10:00

Device Physics and Simulation

M07: "Atomistic" Simulation of AlGaAs/InGaAs/GaAs pHEMTs
A. P. A. Baleeiro and P. C. M. Machado

M08: Numerical Analysis of the Quantum STUB Transistor
A. B. Guerra and E. J. P. Santos

M09: State Diagram Simulations of SET Circuits Using SPICE
R. Van de Haar and J. Hoekstra

M10: On the Modelling of the Dark Current Characteristics of Heterodimensional Schottky Photodiodes
R. Ragi, M. A. Romero and B. Nabet

10:00 to 10:20

Break

10:20

to

12:00

Low Temperature

IM02: Low Temperature Electronics: From Fundamental Physics to Emerging Silicon Technologies (Invited Paper)
Cor Claeys, IMEC, Belgium

M11: A Study on the Self-Heating Effect in Deep-Submicrometer Partially Depleted SOI MOSFETs at Low Temperatures
M. A. Pavanello, J. A. Martino, E. Simoen, A. Mercha, C. Claeys and K. De Meyer

M12: Performance Analysis of Single-Electron Winner-Take-All Network Circuits
J. Guimarães and J. C. da Costa

12:00 to 14:00

Lunch

14:00

to

15:40

SOI - 2

M13: Analysis of the Capacitance vs. Voltage in Graded Channel SOI Capacitor
V. Sonnenberg and J. A. Martino

M14: Analysis on GC SOI MOSFET Analog Parameters at High Temperatures
M. Galeti, M. A. Pavanello and J. A. Martino

M15: Study of Series Resistance and Effective Channel Length Behavior Comparing Graded-Channel and Conventional SOI nMOSFETs
G. F. de Almeida, A. S. Nicolett and J. A. Martino

M16: An Improved Current Model for Edgeless SOI MOSFETS
R. Giacomini and J. A. Martino

15:40 to 16:00

Break

16:00

to

17:30

Panel 2 (in English)

Future Systems Design: The Convergence of Technology, Design and Tools

    Moderator: Wolfgang Rosenstiel

    Panelists: Cor Claeys, IMEC, Belgium

                    Santanu Dutta, Philips Semiconductors, USA

                    Patrick Lysaght, Xilinx , USA

                    Grant Martin, Cadence Berkeley Labs, USA

20:00

Conference Dinner


Thursday, September 11, 2003

8:20

to

10:00

Process Technology - 2

M17: Characterization of Electrospinning Process Using Blends of Polyacrylonitrile and Carbon Particles
A. N. R.da Silva, R. Furlan, I. Ramos, M. L. P. da Silva, E. Fachini, J. J. Santiago-Avilés

M18: Selective Silicon Nitride Etching by ECR Plasmas Using SF6 and NF3 Based Gas Mixtures
C. Reyes-Betanzo, S. A. Moshkalyov, J. W. Swart and A. C. S. Ramos

M19: Study of Power Balance in Electronegative Capacitively Coupled Plasmas
L. Swart, P. Verdonck and S. A. Moshkalyov

M20: Synthesis of Carbon Nanotubes by Plasma-Enhanced Chemical Vapor Deposition
S. A. Moshkalyov, C. Reyes-Betanzo, J. W. Swart and A. C. S. Ramos

10:00 to 10:20

Break

10:20

to

12:00

Device Characterization

IM3: The Integral Function Method: A New Method to Determine the Non-Linear Harmonic Distortion (Invited Paper)
A. Cerdeira, M. A. Alemán, M. Estrada, D. Flandre, B. Parvais and G. Picún, CINVESTAV, Mexico

M21: Determination of the Silicon Film Thickness and Back Oxide Charge Density on Graded-Channel SOI nMOSFETs
A. S. Nicolett, J. A. Martino and M. A. Pavanello

M22: ESD Defect Localization and Analysis Using Pulsed OBIC Techniques
T. Beauchêne, D. Lewis, D. Tremouilles, F. Essely, P. Perdu and P. Fouillat

12:00 to 14:00

Lunch

14:00

to

15:40

Sensors and Actuators
M23: Integrated Termopiles for Infrared Sensing
W. R. Mendes, H. E. M. Peres and F. J. Ramirez-Fernandez

M24: Porous Silicon Processing for Enhancing Thin Silicon Membranes Fabrication
M. O. S. Dantas, E. Galeazzo, H.E.M. Peres and F. J. Ramirez-Fernandez

M25: Gold Microwires Applied to Cardiac Potential Detection
M. B. A. Fontes and I. A. Cestari

M26: Simulations of Silicon Microstructure for Preconcentration of Metallic Ions
J. A. F. da Silva, R. Furlan, E. W. Simões, M. L. P. da Silva and M. T. Pereira

15:40 to 16:00

Break

16:00

to

17:30

Panel 3 (in Portuguese)

Como alavancar a pesquisa e desenvolvimento em Microeletrônica no Brasil?

    Moderator: Wilhelmus van Noije, USP, Brazil

    Panelists:  Reinaldo Bergamaschi, IBM Research , USA

                    Carlos H. de Brito Cruz, UNICAMP, Brazil

                    José R. Leite, CNPq , Brazil

                    Sergio M. Rezende, FINEP, Brazil

                    Flavio R. Wagner, UFRGS / SBC, Brazil