TUTORIALS
This
year we have already confirmed the prominent speakers:
- Magali Estrada
del Cueto - CINVESTAV, Mexico
Dielectrics For Submicrometric Devices
Details...
- Jean-Pierre
Colinge - University of California, USA
Silicon-on-Insulator: Materials and Devices
Details...
- Cor Claeys
- IMEC, Belgium
Submicron Silicon Technologies
Details...
Dielectrics
For Submicrometric Devices
Magali Estrada del Cueto - Center of Research and Advanced Studies
(CINVESTAV), Mexico.
Abstract:
We present the
state of the art of present ultra thin SiO2 and oxynitride layers of less
than 3 nm, used as gate dielectrics for MOS devices with submicrometric
channel length and their limitations for further channel length reduction.
Conduction
mechanisms in ultrathin gate dielectrics are analyzed. Other problems
present in ultrathin gate dielectrics of less than 2.5 nm for MOS devices
are discussed.
The
necessity of alternative high dielectric constant gate dielectrics is
analyzed, as well as what to look for in them. We review main materials
under research and fabrication techniques obtained by different authors.
We detail results on room temperature plasma oxidation and photo-CVD techniques
developed at our laboratory for single and multilayer gate structures.
Advantages and disadvantages of single and multilayer gate structures
are also discussed.
Presentation
also includes a brief look to the problematic of low k dielectrics.
Short
Biography:
Magali
Estrada del Cueto - Professor at the Section of Solid State Electronics,
of the Department of Electrical Engineering at the Center of Research
and Advanced Studies of Mexico D.F. since 1995. Since 1966, engaged in
teaching, research and development on Microelectronics, including technology,
design and characterization of MOS devices and circuits; methods of deposition
of dielectric and semiconductor layers and their characterization; amorphous
TFT and thick PIN diodes for radiation detectors. Author and co-author
of more than 150 international publications. IEEE Senior Member. EDS/IEEE
Distinguished Lecturer.
Silicon-on-Insulator:
Materials and Devices
Jean-Pierre Colinge - University of California, Davis, USA
Abstract:
Silicon-on-Insulator
(SOI) technology has greatly evolved and has now become a commercial success.
From a materials point of view there exist now a process to fabricate
SOI wafers in large quantities, such that industrial production of SOI
chips is made possible. The fabrication techniques for producing modern
SOI materials (SIMOX, UNIBOND and ELTRAN) will be described. The first
SOI transistors date back to 1964. They were partially depleted devices
fabricated on Silicon-on-Sapphire (SOS) substrates. SOS technology was
successfully used for numerous military and civilian applications and
is still being used to realize commercial HF circuits in fully depleted
CMOS. Once the first SOI substrates (the insulator is now silicon dioxide)
were available for experimental MOS device fabrication, partially depleted
technology the natural choice derived from SOS experience. Partially depleted
CMOS continues to be used nowadays and several commercial IC manufacturers
have SOI products and product lines such as microprocessors (e.g.: AMD,
IBM, Motorola), memory chips (Honeywell). The first fully depleted SOI
MOSFET date back to the early 1980's where it was quickly established
that these devices exhibited superior transconductance, current drive
and subthreshold swing. Fully-depleted SOI technology is being used in
commercial products as well (e.g.: OKI, Peregrine).
To improve
short-channel characteristics and increase current drive, SOI technology
is shifting focus from "classical" single-gate MOSFET architectures
to multiple-gate device structures. This tutorial will trace the history
of single- and multiple-gate SOI MOSFETs and summarize the electrical
characteristics of such devices. The properties of the different types
of SOI MOSFETs will be compared and trends will be extrapolated to try
to envision future SOI device structures.
Short
CV:
Academic experience:
- 1997- : Professor
at the University of California, Davis
- 1991-1997:
Professor at the Université Catholique de Louvain (UCL), Faculty
of Applied Sciences, Department of Electricity (ELEC), Microelectronics
Laboratory (DICE).
- 1990-1991:
Invited professor at the UCL, academic year 1990-1991: 1st semester:
Course on advanced semiconductor device physics; 2nd semester: Course
of (regular) semiconductor device physics
- Feb. 91 -
March 91: Invited professor University of South Florida, Tampa, Florida,
USA. I wrote a report on the challenges of SOI technology for the
Semiconductor Research Corporation.
- Courses and
seminars presented in different universities and research centers
in Japan, USA (MIT, Stanford, Berkeley, MCNC, ...) and Europe. I was
invited twice in japan by the MITI (Japanese Ministery of Trade and
Industry) to present results and prospectives of SOI technology in
Japan.
Professional
experience:
- 1991-1997:
Professor at UCL. Head of the technology group of the Microelectronics
group.
- 1988-1991:
Project leader of the SOI project at IMEC (Inter University Microelectronics
Center) in Leuven, Belgium. Design and fabrication of novel SOI devices
(including radiation-hard devices).
- 1985-1988:
Member technical staff of the Hewlett-Packard Research Labs, Palo
Alto, Calif., USA. Development of a bulk BiCMOS process.
- 1981-1984:
Researcher at the Centre National d'Etudes des Télécommunications
(CNET), Grenoble, France. Development of a technique of laser recrystallisation
for the fabrication of SOI films.
Studies:
- 1984: Ph.
D. in Applied Sciences at the UCL.
- 1980: Electrical
Engineering diploma at the UCL (Summa cum laude).
- 1980: Diploma
of bachelor in philosophy at UCL.
Societies:
- Member of
IEEE (1986), Senior Member of IEEE (1990), IEEE Fellow (1996)
- Member of
the Electrochemical Society (1990).
Awards:
- Biennal Siemens
Award (shared with D. Flandre and A. Terao), 1992 (Belgium)
- Best paper
award at the IEEE SOS/SOI Technology Conf., 1990 (USA)
- Montefiore
Award, 1995 (Belgium)
- Jaumain Award,
1998 (Belgium)
Patents:
- French Patent
81-20839:" Fabrication process for stacked CMOS", E Demoulin,
JP Colinge
- French Patent
81-20838:"Fabrication process for a self-aligned stacked CMOS
inverter with both channels self-aligned with respect to the gate",
E Demoulin, JP Colinge
- US Patent
4,725,561:"Fabrication process of single-crystal silicon islands
dielectrically insulated from one another", M. Haond, JP Colinge,
D. Bensahel, M. Dutartre
- US patent
4,857,476: "Bipolar transistor process using sidewall spacer
for aligning base insert", JP Colinge
- US patent
4,810,664: "Method for making patterned implanted buried oxide
transistors and structures", TI Kamins, JP Colinge, PJ Marcoux,
LM Roylance, JL Moll
- European patent
90202500.6 "Method of manufacturing a field effect transistor
and a semiconductor element", JP Colinge
- Dutch patent
application 8902662 "Compensation of radiation-induced effects
for CMOS", JP Colinge
- US Patent
5,272,369 "Circuit elements with elimination of kink effect",
MH Gao, JP Colinge, C.Claeys
- US patent
5,233,236: "Method and device for compensating drift in a semiconductor
element", JP Colinge
- US patent
6,359,311: "Quasi-surrounding gate and a method of fabricating
a silicon-on-insulator semiconductor device with the same", J.P.
Colinge and C. H. Diaz
- US patent
6,391,752: "A method of fabricating a silicon-on-insulator semiconductor
device with implanted ground plane", J.P. Colinge and C. H. Diaz
Submicron
Silicon Technologies
Cor Claeys - IMEC, Leuven, Belgium
Abstract:
The
International Technology Roadmap for Semiconductors (ITRS) is predicting
the technology evolution for the coming 15 years, required to give
the semiconductor industry a competitive market position. This not
only implies pushing existing process modules to the limits but also
introducing new ones, which most likely will be based on alternative
concepts and/or the use of new materials. This presentation will be
focusing on a selection of these processing challenges.
First
the silicon material requirements will be addressed, including high
quality silicon substrates, epitaxial wafers, thin film SOI, SiGe
and strained silicon. Subsequently some process modules will be discusses
such as e.g. as isolation schemes, gate dielectrics based on high-k
materials, silicides and interconnect schemes. Beside the use of novel
or alternative materials, attention will also be given to equipment
aspects like atomic layer deposition, single wafer processing, flash
annealing, etc.
The
last part will outline the importance of so-called gate engineering,
including metal gates, doubles gate structures, vertical replacement
gates and FinFETS. These approaches are presently extensive studied
and will surely be used for the 45 nm and below emerging silicon technologies.
Short
CV:
Cor
Claeys was born in Antwerp, Belgium. He obtained his Elecrical Engineering
Degree and his Ph.D. at the Catholic University of Leuven, Belgium,
respectively in 1974 and 1979. He was staff member of the ESAT laboratory
before joining IMEC in 1984 as Head of Silicon Processing. Since 1990
he is heading a research group on Radiation Effects, Cryogenic Electronics
and Noise Studies. He is also responsible for Technology Business
Development and Professor in Material Science at the Catholic University
of Leuven. He is author and co-author of more than 500 international
publications, eight book chapters, co-edited a book on "Low Temperature
Electronics", wrote a book on "Radiation Effects in Advanced
Semiconductor Materials and Devices" and co-authored more than
450 contributions at International Conferences (of which 25 invited
presentations since 1990). Editor or co-editor of 20 Conference Proceedings
Volumes. He is member of several societies and committees, of which
the most important are: Chairman of the Executive Committee of the
Electronics Division of the Electrochemical Society, Elected member
of the EDS AdCom, and Chair of the EDS Regions/Chapters. He is a fellow
of the Electrochemical Society, a Senior member of IEEE, and was in1999
elected as Academician and Professor of the International Information
Academy. His main interests are in silicon processing, device physics,
low temperature electronics, radiation physics, submicron silicon
technologies, defect engineering, and low frequency noise.
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