Student
Forum 2003
CHIP IN
SAMPA
São
Paulo, Brazil
September 8-11, 2003
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ADVANCE PROGRAM |
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Abertura e Projetos |
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DESIGN OF ADDER
ARCHITECTURES FOR JPEG COMPRESSION CMOS RF AMPLIFIER
FOR SAW - BASED INTEGRATED SMART SENSOR COMPARING 2'S
COMPLEMENT MULTIPLIERS WITH BINARY AND HYBRID OPERAND ENCODING A GM-C BUMP
EQUALIZER FOR LOW-VOLTAGE APPLICATIONS PLD-BASED GENERATION
OF SPECIAL WAVEFORMS WITH LOW THIRD HARMONIC CONTENT IMPLEMENTATION
OF MONTGOMERY MULTIPLICATION IN A COARSE-GRAINEDED RECONFIGURABLE ARCHITECTURE DESIGN AND DISCRETE
IMPLEMENTATION OF A SIMPLE SIGMA-DELTA ADC |
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Terça-feira, 9 de Setembro de 2003 |
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8:20
to 10:00 |
Projetos |
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PARAMETRIC VHDL
MODELS OF ARBITERS FOR NETWORKS-ON-CHIP XROACH: A TOOL
FOR GENERATION OF EMBEDDED ASSERTIONS GENERAL PURPOSE
FOLDED-CASCODE CMOS OPAMP DESIGN DESIGNING TWO
PARALLEL MULTIPLIER ARCHITECTURES FOR DSP COMPARING SYSTEMC
AND ARCHC THROUGH THE MIPS PROCESSOR MODELING DESCRIBING AND
TESTING ARITHMETICAL CIRCUITS IN A FUNCTIONAL LANGUAGE COMPACT 4-BIT
CARRY LOOK-AHEAD ADDER IN MULTIPLE OUTPUT ECDL GATE ANALYSIS AND
VALIDATION OF A ANALOG COMPARATOR USING CADENCE? ENVIRONMENT |
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16:40
to 18:00 |
Posters |
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LAMPIÃO
= LDN - ARQUITETURA DE MICROCONTROLADOR E PROPRIEDADE INTELECTUAL PARA
AUTOMAÇÃO ERROR MINIMIZATION
OF 2-D DCT AND QUANTIZATION OPERATIONS FOR A GRAY SCALE IMAGES JPEG
COMPRESSOR CHARACTERIZATION
OF INDUCTIVELY COUPLED ARGON PLASMAS DEVELOPMENT
OF A COMB-DRIVE´S FAILURES IDENTIFICATION METHODOLOGY TEST SCHEDULING
AND BENCHMARK IMPLEMENTATIONS FOR THE ANALYSIS OF SOC TESTING A LABORATORY
IN ANALOG COMMUNICATION SYSTEMS APPLE PARROT:
A CIRCUIT PARTITIONER LOGIC COMPLETION
DETECTION IN PROGRAMMABLE LOGIC DEVICES MICROKERNEL
FOR NODES OF WIRELESS SENSOR NETWORKS MIDDLEWARE FOR
WIRELESS SENSOR NETWORKS DEVELOPMENT
OF A COMPUTATIONAL TOOL FOR THE EVALUATION OF EMC PARAMETERS IN INTEGRATED
CIRCUITS – COMPARISON AMONG SOME CAPACITANCE MODELS JHADES: OPEN
DESIGN ENVIRONMENT ON JAVA A 0-10DBM, 915-927.5
MHZ, 0.35 ÌM CMOS CLASS E POWER AMPLIFIER WITH XINGÓ:
A PROTOTYPING PLATFORM WITH PROCESSING CAPABILITIES STUDY OF DEVICE
PARAMETER EXTRACTION IN SOI NMOSFETS AN ASSEMBLER
PROGRAM FOR A 16 BIT SOC RISC PROCESSOR DEVELOPMENT
OF A VIRTUAL INSTRUMENT APPLIED TO HEAVY METAL DETECTION IN WATER A RAPID PROTOTYPING
METHODOLOGY FOR EMBEDDED SYSTEMS DESIGN A 8051 µC
FUNCTIONAL RTL DESCRIPTION USING SYSTEMC FOR PLATFORM BASED DESIGN |
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Processos e Dispositivos |
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SHALLOW N +
-P JUNCTIONS IN SI AND SIMOX DESIGN AND DEVELOPMENT
OF A TWO COORDINATE POSITION SENSITIVE PHOTODETECTOR SHALLOW P+N-JUNCTION
FORMATION IN SI BY PRE-AMORPHIZATION WITH SN STUDY OF THE
ETU PROCESSES IN ND3+ DOPED LEAD FLUORBORATE GLASSES ELECTRICAL CHARACTERIZATION
OF SOI MOSFET AT HIGH TEMPERATURE IMPLEMENTATION
OF A CONTINUOUS MODEL OF ADVANCED SOI MOS TRANSISTORS USING MATLAB SILICON FILM
AND FRONT OXIDE THICKNESS EXTRACTION ON SOI DEVICES USING TWO DIFFERENT
TECHNIQUES ANALYTIC MODEL
CORRECTION FOR LOW TEMPERATURE TWO-DIMENTIONAL SIMULATION NOISE CHARACTERIZATION
OF ANALOG DEVICES LEAD FLUORBORATE
GLASSES DOPED WITH ER 3+ FOR OPTOELECTRONIC DEVICES |
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Projetos |
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IMPLEMENTATION
OF ARBITER CIRCUIT FOR ASYNCHRONOUS DESIGN A TINY JPEG
DECOMPRESSOR MONTE CARLO
AND CORNER SIMULATIONS FOR ANALOG VLSI DESIGN FREQUENCY SYNTHESIZER
FOR A SYSTEM-ON-CHIP RF TRANSCEIVER DEVELOPMENT
OF A MICRO-CONTROLLED HEAT SYSTEM APPLIED TO THERMIC WATER BEDS IN HOSPITALS DEDICATED INSTRUCTIONS
TO SUPPORT MULTIPROCESSING ON A EMBEDDED JAVA ARCHITECTURE NEW APPLICATIONS
OF THE AUTOMATIC LAYOUT GENERATION TOOL CDF-2 OPTIMIZATION
OF THE MOVE ARCHITECTURE APPLIED TO DSP UTILIZING BIT- SERIAL MULTIPLIERS |
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