Student Forum 2003
CHIP IN SAMPA

São Paulo, Brazil
September 8-11, 2003

ADVANCE PROGRAM

Segunda-feira, 8 de Setembro de 2003

8:30

to

10:00

Abertura e Projetos

DESIGN OF ADDER ARCHITECTURES FOR JPEG COMPRESSION
Roger Endrigo Carvalho Porto (UFPEL) e Luciano Volcan Agostini (UFPEL).

CMOS RF AMPLIFIER FOR SAW - BASED INTEGRATED SMART SENSOR
Victor Miranda da Silva (UFPE) e Edval J.P. Santos (UFPE).

COMPARING 2'S COMPLEMENT MULTIPLIERS WITH BINARY AND HYBRID OPERAND ENCODING
Leonardo L. de Oliveira (UFSM), Marcos Boschetti (UFRGS),
Eduardo da Costa (UCPEL), Sergio Bampi (UFRGS) e João Baptista (UFSM).

A GM-C BUMP EQUALIZER FOR LOW-VOLTAGE APPLICATIONS
R. Galembeck (UFSC), J. A. de Lima (UNESP) e M. C. Schneider (UFSC).

PLD-BASED GENERATION OF SPECIAL WAVEFORMS WITH LOW THIRD HARMONIC CONTENT
Edval J. P. Santos (UFPE) e Khyale S. Nascimento (UFPE).

IMPLEMENTATION OF MONTGOMERY MULTIPLICATION IN A COARSE-GRAINEDED RECONFIGURABLE ARCHITECTURE
Arnaldo Azevedo (UFRN), Rodrigo Soares (UFRN) e Ivan Saraiva Silva (UFRN).

DESIGN AND DISCRETE IMPLEMENTATION OF A SIMPLE SIGMA-DELTA ADC
Edgar Mauricio Camacho (UFSC), Luis Henrique Spiller (UFSC) e Luigi Carro (UFRGS).


Terça-feira, 9 de Setembro de 2003

8:20

to

10:00

Projetos

PARAMETRIC VHDL MODELS OF ARBITERS FOR NETWORKS-ON-CHIP
Frederico G. M. E. Santo (UNIVALI) e Cesar A. Zeferino (UNIVALI).

XROACH: A TOOL FOR GENERATION OF EMBEDDED ASSERTIONS
Márcia C. Marra de Oliveira (UFMG), José Augusto M. Nacif (UFMG),
Claudionor Nunes Coelho Jr. (UFMG) e Antônio Otávio Fernandes (UFMG).

GENERAL PURPOSE FOLDED-CASCODE CMOS OPAMP DESIGN
Edgar Mauricio Camacho (UFSC), Luiz Alberto Pasini Melek (UFSC) e
Márcio Cherem Schneider (UFSC).

DESIGNING TWO PARALLEL MULTIPLIER ARCHITECTURES FOR DSP
Leomar S. Rosa Jr. (UFRGS), Marcos R. Boschetti (UFRGS), Émerson B. Hernandez (UFRGS), André B. Soares (UFRGS), Eduardo Costa (UCPEL), Sergio Bampi (UFRGS).

COMPARING SYSTEMC AND ARCHC THROUGH THE MIPS PROCESSOR MODELING
Marcio Rogério Juliato (UNICAMP) e Paulo Cesar Centoducatte (UNICAMP).

DESCRIBING AND TESTING ARITHMETICAL CIRCUITS IN A FUNCTIONAL LANGUAGE
Frederico A. Mameri (UFU), Hélio D. Batista Júnior (UFU), Nélio M. M. Alves (UFU) e
Sérgio M. Schneider (UFU).

COMPACT 4-BIT CARRY LOOK-AHEAD ADDER IN MULTIPLE OUTPUT ECDL GATE
M. C. B. Osório (UFRGS), R. E. B. Poli (UFRGS), A. I. Reis (UFRGS) e R. P. Ribas (UFRGS).

ANALYSIS AND VALIDATION OF A ANALOG COMPARATOR USING CADENCE? ENVIRONMENT
Juan Pablo Martinez Brito (UFRGS), Fernando Paixão Cortes (UFRGS) e Sergio Bampi (UFRGS).

 

16:40

to

18:00

Posters

LAMPIÃO = LDN - ARQUITETURA DE MICROCONTROLADOR E PROPRIEDADE INTELECTUAL PARA AUTOMAÇÃO
Hércules S. Padilha Jr. (UFPE) e Edval J. P. Santos (UFPE).

ERROR MINIMIZATION OF 2-D DCT AND QUANTIZATION OPERATIONS  FOR A GRAY SCALE IMAGES JPEG COMPRESSOR
 Bruno Silveira Neves (UFPEL) e Luciano Volcan Agostini (UFPEL).

CHARACTERIZATION OF INDUCTIVELY COUPLED ARGON PLASMAS
 Bruno S. Rodrigues (EPUSP), Laura Swart (EPUSP) e Patrick Verdonck (EPUSP).

DEVELOPMENT OF A COMB-DRIVE´S FAILURES IDENTIFICATION METHODOLOGY
Daniel Gerhardt (UFRGS), I. Iturrioz (UFRGS) e R. P. Ribas (UFRGS).

TEST SCHEDULING AND BENCHMARK IMPLEMENTATIONS FOR THE ANALYSIS OF SOC TESTING
Rodrigo Boccasius (UFRGS), Érika Cota (UFRGS) e Marcelo Lubaszewski (UFRGS).

A LABORATORY IN ANALOG COMMUNICATION SYSTEMS
 Pablo Dutra da Silva (UFSC) e Carlos Galup-Montoro (UFSC).

APPLE PARROT: A CIRCUIT PARTITIONER
Diogo Fiorentin (UFRGS), Renato Hentschke (UFRGS) e Ricardo Reis (UFRGS).

LOGIC COMPLETION DETECTION IN PROGRAMMABLE LOGIC DEVICES
 C. A. Sampaio (UFRGS), R. T. Vaz da Silva (UFRGS), A. I. Reis (UFRGS) e
R. P. Ribas (UFRGS).

MICROKERNEL FOR NODES OF WIRELESS SENSOR NETWORKS
Vinícius Coelho de Almeida (UFMG), Breno Augusto Dias Vitorino (UFMG),
Luiz Filipe Menezes Vieira (UFMG), Marcos Augusto Menezes Vieira (UFMG),
Antônio Otávio Fernandes (UFMG), Diógenes Cecílio da Silva (UFMG) e
Claudionor Nunes Coelho Jr. (UFMG).

MIDDLEWARE FOR WIRELESS SENSOR NETWORKS
Breno A. D. Vitorino (UFMG), Luiz F. M. Vieira (UFMG), Marcos A. M. Vieira (UFMG), Vinícius C. de Almeida (UFMG), Antônio O. Fernandes (UFMG), Diógenes C. da Silva (UFMG) e Claudionor N. C. Júnior (UFMG).

DEVELOPMENT OF A COMPUTATIONAL TOOL FOR THE EVALUATION OF EMC PARAMETERS IN INTEGRATED CIRCUITS COMPARISON AMONG SOME CAPACITANCE MODELS
 G. S. Beserra (UNB), R. M. D. Rangel (UNB) e L. R. A. X. de Menezes (UNB).

JHADES: OPEN DESIGN ENVIRONMENT ON JAVA
Ulisses Chieppe (UFV), Giliardo Freitas (UFV), Cristiano Biancardi (UFV) e Ricardo Santos Ferreira (UFV).

A 0-10DBM, 915-927.5 MHZ, 0.35 ÌM CMOS CLASS E POWER AMPLIFIER WITH
DIGITAL POWER CONTROL AND DIRECT MODULATION

Leandro Santana Assunção (UNB) e José Camargo da Costa (UNB).

XINGÓ: A PROTOTYPING PLATFORM WITH PROCESSING CAPABILITIES
Marcio Rogério Juliato (UNICAMP) e Paulo Cesar Centoducatte (UNICAMP).

STUDY OF DEVICE PARAMETER EXTRACTION IN SOI NMOSFETS
Artur Gasparetto Paiola (EPUSP), Marcelo Antonio Pavanello (EPUSP) e João Antonio Martino (EPUSP).

AN ASSEMBLER PROGRAM FOR A 16 BIT SOC RISC PROCESSOR
Ryan M. D. Rangel (UNB), Juliana Z. F. Diniz (UNB), Ricardo R. Linder (UNB), Geraldo M. Benício Jr.; Adson F. da Rocha (UNB) e José C. da Costa (UNB).

DEVELOPMENT OF A VIRTUAL INSTRUMENT APPLIED TO HEAVY METAL DETECTION IN WATER
Juliana Lopes Cardoso (FATEC) e Marcelo Bariatto Andrade Fontes (EPUSP).

A RAPID PROTOTYPING METHODOLOGY FOR EMBEDDED SYSTEMS DESIGN
Carlos Eduardo Monteiro Rodrigues (UFPE), Gustavo José Câmara Cavalcanti (UFPE), Marcus Vinícius Lima e Machado (UFPE), Paulo Roberto Oliveira Santana Filho (UFPE), Viviane Cristina Oliveira Aureliano (UFPE) e Manoel Eusébio de Lima (UFPE).

A 8051 µC FUNCTIONAL RTL DESCRIPTION USING SYSTEMC FOR PLATFORM BASED DESIGN
Diogo José Costa Alves (UFPE), Tiago Sampaio Lins (UFPE), Silvio Veloso Freire Neto (UFPE) e Edna Barros (UFPE).


Quarta-feira, 10 de Setembro de 2003

8:20

to

10:00

Processos e Dispositivos

SHALLOW N + -P JUNCTIONS IN SI AND SIMOX
 M. Dalponte (UFRGS), H. Boudinov (UFRGS) e J. P. Souza (UFRGS).

DESIGN AND DEVELOPMENT OF A TWO COORDINATE POSITION SENSITIVE PHOTODETECTOR
Ricardo Cunha Gonçalves da Silva (UFRGS) e Henri Ivanov Boudinov (UFRGS).

SHALLOW P+N-JUNCTION FORMATION IN SI BY PRE-AMORPHIZATION WITH SN
 E.M. Scherer (UFRGS) e H. Boudinov (UFRGS).

STUDY OF THE ETU PROCESSES IN ND3+ DOPED LEAD FLUORBORATE GLASSES
 B. L. S. de Lima (FATEC), L. C. Courrol (FATEC),  L. R. P. Kassab (FATEC), V. D. Del Cacho, L. Gomes (FATEC) e N. U. Wetter (FATEC).

ELECTRICAL CHARACTERIZATION OF SOI MOSFET AT HIGH TEMPERATURE
Carolina Davanzzo Gomes dos Santos (EPUSP), João Antonio Martino (EPUSP) e Marcelo Antonio Pavanello (EPUSP).

IMPLEMENTATION OF A CONTINUOUS MODEL OF ADVANCED SOI MOS TRANSISTORS USING MATLAB
Michelly de Souza (EPUSP) e Marcelo Antonio Pavanello (EPUSP).

SILICON FILM AND FRONT OXIDE THICKNESS EXTRACTION ON SOI DEVICES USING TWO DIFFERENT TECHNIQUES
Michele Rodrigues (USP), A. S. Nicolett (USP) e J. A. Martino (USP).

ANALYTIC MODEL CORRECTION FOR LOW TEMPERATURE TWO-DIMENTIONAL SIMULATION
Sára Elizabeth de Souza Costa (EPUSP) e Marcelo Antonio Pavanello (EPUSP).

NOISE CHARACTERIZATION OF ANALOG DEVICES
 C.D.C. Caetano (UFSC) e C. Galup-Montoro (UFSC).

LEAD FLUORBORATE GLASSES DOPED WITH ER 3+ FOR OPTOELECTRONIC DEVICES
 R. Seragioli (FATEC), L. R. P. Kassab (FATEC) e L.C.Courrol (FATEC).


Quinta-feira, 11 de Setembro de 2003

8:20

to

10:00

Projetos

IMPLEMENTATION OF ARBITER CIRCUIT FOR ASYNCHRONOUS DESIGN
R. T. Vaz da Silva (UFRGS), C. A. Sampaio (UFRGS), M. C. B. Osório (UFRGS), A. I. Reis (UFRGS) e R. P. Ribas (UFRGS).

A TINY JPEG DECOMPRESSOR
José Porfírio A. de Carvalho (UNB), Roberto Silva Cantanhêde (UNB) e Ricardo P. Jacobi (UNB).

MONTE CARLO AND CORNER SIMULATIONS FOR ANALOG VLSI DESIGN
Fernando Paixão Cortes (UFRGS), Alessandro Girardi (UFRGS), Felipe Ródio (UFRGS), Eric Fabris (UFRGS) e Sergio Bampi (UFRGS).

FREQUENCY SYNTHESIZER FOR A SYSTEM-ON-CHIP RF TRANSCEIVER
 Rafael R. P. Soares (UNB) e José C. da Costa (UNB).

DEVELOPMENT OF A MICRO-CONTROLLED HEAT SYSTEM APPLIED TO THERMIC WATER BEDS IN HOSPITALS
Jair Lins de Emeri Jr. (FATEC) e Marcelo Bariatto Andrade Fontes (EPUSP).

DEDICATED INSTRUCTIONS TO SUPPORT MULTIPROCESSING  ON A EMBEDDED JAVA ARCHITECTURE
 L.S.Rosa Jr. (UFRGS), A.C.Beck Fo. (UFRGS), F.R.Wagner (UFRGS), L.Carro (UFRGS), A.S.Carissimi (UFRGS) e A.I.Reis (UFRGS).

NEW APPLICATIONS OF THE AUTOMATIC LAYOUT GENERATION TOOL CDF-2
 Felipe R. Schneider (UFRGS), João D. Togni (UFRGS), Renato E. B. Poli (UFRGS), Júlio C. Silvello (UFRGS), Renato P. Ribas (UFRGS) e André I. Reis (UFRGS).

OPTIMIZATION OF THE MOVE ARCHITECTURE APPLIED TO DSP UTILIZING BIT- SERIAL MULTIPLIERS
 Igor Gavazzi Vazzoler (UFSC) e Luigi Carro (UFRGS).