Ilha de Santo Aleixo
and Time: Friday, 11:00-12:00
and Test Challenges in SoC Designs
Augusto Dueñas M.
(System-on-Chip) designs have introduced several new challenges for the
and test disciplines. Besides the ever-growing functional complexity, we
from several clock domains and low-power modes to all sorts of IP blocks
peripherals, analog functions and different kinds of embedded memories.
The reuse of 3rd
IP may help accelerating the design of new products, but it usually does
not help the
verification and it may even add to its complexity. Also, the same die
may be used in
packages with different number of pins and bond-out options. This presentation
and other verification and test challenges. It also describes what tools,
the industry is currently using to cope with them, and finalizes outlining