Room:
Ilha de Santo Aleixo
Date
and Time: Friday, 11:00-12:00
Verification
and Test Challenges in SoC Designs
César
Augusto Dueñas M.
Freescale
Semiconductor Inc.
Jaguariúna,
Brazil
Abstract
SoC
(System-on-Chip) designs have introduced several new challenges for the
functional
verification
and test disciplines. Besides the ever-growing functional complexity, we
need to
manage
from several clock domains and low-power modes to all sorts of IP blocks
like processors,
complex
peripherals, analog functions and different kinds of embedded memories.
The reuse of 3rd
party
IP may help accelerating the design of new products, but it usually does
not help the
functional
verification and it may even add to its complexity. Also, the same die
may be used in
several
packages with different number of pins and bond-out options. This presentation
will discuss
these
and other verification and test challenges. It also describes what tools,
techniques and
methodologies
the industry is currently using to cope with them, and finalizes outlining
some
future
directions. |