David Z. Pan
Department of Electrical and Computer Engineering
The University of Texas at Austin, TX 78712
Title:
Lithography Friendly Routing: From Construct-by-Correction to Correct-by-Construction
Abstract:
Deep sub-wavelength lithography, e.g., using the 193nm lithography to print 45nm, 32nm, and even 22nm
integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling.
Lithography printability is strongly layout dependent. Routing is the last major physical design
step before tapeout, thus it plays an important role in addressing the overall circuit manufacturability
and product yield. This talk will discuss some recent advancement of lithography friendly routing from
post-routing hotspot fixing (construct-by-correction) to during-routing hotspot avoidance (correct-by-construction)
guided by predictive post-OPC lithography metrics. We will compare the quality of results and runtime of these
approaches, and show how to combine them. We will also discuss the emerging research needs, such as double
patterning lithography for 32nm and 22nm nodes and how routing may cope with them.
Biography:
David Pan received his Ph.D. in computer science (with honor) from UCLA in 2000.
He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to
2003. He is an Associate Professor with ECE Department of the University of
Texas at Austin, where he leads the UT Design Automation (UTDA) Lab. His
research is mainly focused on nanometer physical CAD and design for manufacturability.
He is also interested in the emerging issues in CAD. He holds 5 U.S. patents and
has published over 80 technical papers. He is an Associate Editor for IEEE
Transactions on CAD, IEEE Transactions on VLSI, IEEE Transactions on CAS-I,
and IEEE CAS Society Newsletter. He is on the DFM committee of the International
Technology Roadmap for Semiconductor (ITRS). He has served in the program committees
of major VLSI/CAD conferences including ICCAD, ISPD, DATE, ASPDAC, ISQED, and ISCAS.
He is the ISPD 08 General Chair, 2007 IEEE/CANDE Workshop Chair, ISPD 07
Program Chair, CAD Track Co-Chair for ISCAS 2006 and 2007, and Design of
Reliable Circuits and Systems Chair for ISQED 2007/2008. He has received a number of
awards for his research contributions, including the ACM/SIGDA Outstanding New Faculty
Award, NSF CAREER Award, SRC Inventor Recognition Award, IBM Faculty Awards three times,
several Best Paper Award Nominations at DAC/ASPDAC, SRC Techcon Best Paper in Session
Award, and ISPD 2007 Routing Contest Awards. He is a Cadence Distinguished Speaker in
2007, and an IEEE CAS Society Distinguished Lecturer for 2008-2009. |
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