David Z. Pan
Department of Electrical and Computer Engineering The University of Texas at Austin, TX 78712
Title:
"Synergistic Modeling and Optimization for Nanometer IC Design/Manufacturing Integration"
Abstract:
Nanometer IC design and manufacturing are facing unprecedented grand challenges for 45nm and beyond,
according to ITRS. On one hand, many entangled physical effects continue to pose tremendous challenges to reach
design closure with stringent turn-around-time; on the other hand, design closure no longer guarantees manufacturing
closure. The conventional contracts between design and fab through design rules are breaking, due to deep sub-wavelength
lithography and growing process variations. Thus design/manufacturing integration and co-optimization will become more and more
important. To enable true design/process integration, it is crucial to be able to model proper manufacturing/variability/yield metrics,
and feed them upstream at various physical design implementation stages. This lecture will present synergistic modeling and optimization
issues on both physical and electrical design for manufacturing (DFM). We will seek to address DFM from its root causes, in a holistic manner through better manufacturing for design (e.g., variation aware lithography modeling and optical proximity correction), manufacturing-design interface (e.g., predictive silicon modeling and variational circuit analysis), and true design for manufacturing (e.g., manufacturability aware routing and variational aware clock synthesis).
Biography:
David Z. Pan received his Ph.D. in computer science (with honor) from UCLA in 2000. He was a
Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is an Associate Professor
at the Department of Electrical and Computer Engineering, University of Texas at Austin, where he directs the UT
Design Automation (UTDA) Lab. His research is mainly focused on nanometer physical CAD and design for manufacturability.
He is also interested in design/CAD of emerging technologies. He holds 5 U.S. patents and has published over 80 technical papers.
He has served as an Associate Editor for IEEE Transactions on CAD (2006-), IEEE Transactions on VLSI Systems (2007-),
IEEE Transactions on CAS-I (2008-), IEEE Transactions on CAS-II (2006-2007), and IEEE CAS Society Newsletter (2007-). He is on the DFM
committee of the International Technology Roadmap for Semiconductor (ITRS). He has served in the program committees of major
VLSI/CAD conferences including ICCAD, ASPDAC, DATE, ISPD, ISQED, and ISCAS. He is the 2007 IEEE/CANDE Workshop Chair, Program/General
Chair for ISPD 2007/2008, CAD Track Co-Chair for ISCAS 2006 and 2007. He has received a number of awards for his research contributions,
including the ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Awards (2000 and 2008),
IBM Faculty Awards (2004 to 2006), IBM Research Bravo Award (2003), Best Paper Award Nominations at DAC (2006) and ASPDAC (2006 and 2008),
ISPD 2007 Global Routing Contest Awards, Best Paper in Session
Award at SRC Techcon (1998 and 2007), and ACM Recognition of Service Award (2007). He is a Senior Member of IEEE.
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