Erika Cota - PPGC - Computer Science Dept. - Universidade Federal do Rio Grande do Sul
Marcelo Lubaszewski - Electrical Eng. Dept.- Universidade Federal do Rio Grande do Sul
Design Manager at Texas Instruments Inc. and a Member Grade Technical Staff
Title:
"Reliability, Availability and Serviceability of Networks-on-Chip."
Abstract:
This tutorial presents an overview of the issues related to the test, diagnosis and fault-tolerance of NoC-based systems. First, the characteristics of the NoC design (topologies, structures, routers, wrappers, and protocols) are presented, as well as a summary of the terms used in the field and an overview of the existing industrial NoCs is given. Then, the challenges to test, diagnose and tolerate faults in a NoC-based systems are discussed. Current test strategies are then presented: re-use of on-chip network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware testing. In addition, the challenges and solutions for the NoC (interconnects, routers, and network interface) test and diagnosis are presented. Finally, since quality-of-service is one of the main challenges for the NoC use, fault tolerance techniques for the NoC are discussed.
Biography:
Erika Cota is currently an associate professor at the Computer Science Dept. of Universidade Federal do Rio Grande do Sul (UFRGS), in Porto Alegre, Brazil, where she participates in the Test and Reliability of Integrated Systems Group and in the Embedded Systems Laboratory. Érika got her BS in Computer Science in 1994 from Universidade Federal de Minas Gerais. Subsequently she got her Masters and Doctorate in Computer Science from Universidade Federal do Rio Grande do Sul in 1997 and 2003, respectively. During her PhD. she had a 9-months internship at the Reliable System Synthesis Group at University of California, San Diego. She has also worked as invited researcher at the TIMA Laboratory and the Laboratoire d´Informatique, Robotique et Microélectronique de Montpellier, both in France. Her research interests include the test and design for test of hardware and software systems, test of embedded systems, test planning, and fault tolerance of integrated systems. She has published over 50 papers in international journals and conferences on these topics. In 2003 Érika received the TTTC Naveena Nagi Award with a paper on NoC-based SoC testing.
Marcelo Lubaszewski received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1986 and 1990, respectively. In 1994, he received the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), France. In 2001, he joined the Laboratoire d´Informatique, Robotique et Microélectronique de Montpellier in France as an Invited Researcher for 3 months and, in 2004, the Instituto de Microelectrónica de Sevilla (IMSE) in Spain for 1 year. He is currently with UFRGS, where he has been an Associate Professor since 1990. His primary research interests include design and test of mixed-signal, micro-electro-mechanical, core-based and NoC-based systems, self-checking and fault-tolerant architectures, and computer-aided testing. He has published over 150 papers in international journals and conferences on these topics. Dr. Lubaszewski has served as a Guest Editor of the Journal of Electronic Testing: Theory and Applications, of the Microelectronics Journal and as an Associate Editor of the Design and Test of Computers Magazine. He is presently a member of the Editorial Board of the VLSI Journal and a lecturer for Latin America in the frame of the IEEE Computer Society Distinguished Visitors Program. In the last four years, he has also been serving the IEEE CS Test Technology Technical Council as the Chair of the Latin-America Regional.
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