IEEE CAS Tutorials >> Paul Jespers
Paul Jespers

Title:
"Sizing CMOS circuits by means of the gm/ID methodology and a compact model."

Abstract:
The gm/ID sizing methodology. Sizing the Intrinsic Gain Stage by means of experimental data or a model like the E.K.V./A.C.M. model. Sizing short channel devices with parameters that are functions of bias conditions. Parameter acquisition, accuracy, examples. Application to the sizing of low-power low-voltage CMOS circuits like the Miller Op. Amp, Barranco's current sources, etc .

Biography:
Paul Jespers, received the Electrical and Civil Engineer degree from the Université Libre de Bruxelles (ULB) in1953 and the Doctorate in Applied Sciences from the Université Catholique de Louvain (UCL), Be, in 1959. He started working in the domain of radio interference instrumentation. He joined the Electrical Department of Applied Sciences Faculty of the UCL in 1959, where he started the Microelectonics Laboratory mid 60's. Visiting Professor at Universities in France, Italy, Spain, U.S.A, Latin America, Australia, China and India where he was appointed UNIDO expert. Prof Jespers is an IEEE Fellow, Doctor Honoris Causa from U.C.Cordoba University (Argentina) and F.P.Ms (Belgium). He is now Emeritus Professor of UCL. Prof Jespers contributed to several startup electronic industries in the Belgium.