Tutorials & Invited

Keynotes


	Lessons from Brain Connectivity for Future Interconnect in ICs Jan Rabaey University of California at Berkeley - UCB, USA September 2^nd, Wednesday, 08:40 to 09:40

	Abstract: TBD

	Short Bio: Jan Rabaey received his Ph.D degree in applied sciences from the Katholieke Universiteit Leuven, Belgium. In 1987, he joined the faculty of the Electrical Engineering and Computer Science department of the University of California, Berkeley, where he now holds the Donald O. Pederson Distinguished Professorship. He is currently the scientific co-director of the Berkeley Wireless Research Center (BWRC), as well as the founding director of the Berkeley Ubiquitous SwarmLab. Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, sensor networks, configurable ICs and low-power design. His current interests include the conception and implementation of next-generation integrated wireless systems over a very broad range of applications, as well as exploring the interaction between the cyber and the biological world. He is the recipient of a wide range of major awards, amongst which the IEEE CAS Society Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow and a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has been involved in a broad variety of start-up ventures.

	Majority-based Synthesis for Digital Nano-technologies Giovanni de Micheli EPFL, Switzerland September 3^rd, Thursday, 08:40 to 09:40

	Abstract: Logic synthesis/optimization algorithms and tools have been used for over three decades. Still they suffer from various weaknesses, because they were conceived with CMOS AOI static gates in mind, with more primitive computers and storage systems, and without a strong formal basis. The design of large-scale, computation oriented, digital circuits is still a main challenge even with state of the art commercial tools. Because of the convergence of fabrication technologies, the competitive edge in CMOS design resides in its logic-level structuring achieved within synthesis. Moreover, novel nano technologies open new horizons by means of logic gates with enhanced functionality. Thus, more than ever, synthesis technology is a key to exploit technology in the search for the best design. This talk shows the motivation for searching better models and algorithms - as compared to the state of the art - for logic synthesis. A new Boolean algebra and model is shown to be effective for digital circuit optimization for speed, area and power consumption. Experimental results show that the new tool, MIGHTY, outperforms a commercial tool on the three metrics after complete physical design.

	Short Bio: Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering at EPFL. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University. Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 600 technical articles. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics. Prof. De Micheli is the recipient of the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools, of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems, and of other best paper awards.

	A Path towards Average-Case Silicon via Asynchronous Resilient Bundled-Data Design Peter Beerel University of Southern California (USC) in Los Angeles, USA September 4^th, Friday, 08:40 to 09:40

	Abstract: The periodic nature of the global clock in traditional synchronous designs forces circuits to be margined for the worst possible case of process, voltage, temperature, and data conditions. This constrains the silicon to operate at worst-case frequencies and at conservative supply voltages. Resilient architectures promise to remove these margins, by detecting and correcting timing errors when they occur, thereby creating the potential to achieve real average-case operation. However, synchronous resilient schemes previously proposed can suffer from multiple issues, including being susceptible to metastability and requiring complex changes to the architecture to support replay-based recovery from timing errors. These problems respectively lead to circuit failures and/or incur high timing penalties when errors occur. This keynote explores how the research to achieve average-case silicon evolved over the last two decades. Particularly, it discusses a recently proposed asynchronous bundled-data resilient template called Blade that is robust to metastability issues, requires no replay-based logic, and has low timing error penalties. The Author describes some open issues and new research opportunities this template presents, including automation problems to target average-case operation, specific circuit optimizations to minimize resiliency overhead, and the need for new test procedures to tune delay lines and screen out bad chips.

	Short Bio: Dr. Beerel received his B.S.E. degree in Electrical Engineering from Princeton University, Princeton, NJ, in 1989 and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1991 and 1994, respectively. He joined the the Department of Electrical Engineering--Systems at USC in 1994. Dr. Beerel was the Faculty Director of Innovation Studies at the USC Stevens Institute for Innovation from 2006 to 2008 and is currently the Faculty Director of Innovation and Entrepreneurship in Engineering for the Viterbi School of Engineering. He served as Vice-President of CAD and Verification at Fulcrum Microsystems. In May of 2008, he took a leave of absence from USC and co-founded TimeLess Design Automation with one of his Ph.D. students, Dr. Georgios Dimou. They sold the company in July of 2010 to Fulcrum Microsystems, which was acquired by Intel in 2011 and became its Switch Router Division at which he also worked as Chief Scientist, Technology Development. Dr. Beerel's research interests include a variety of topics in CAD and asynchronous VLSI design. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was Program Co-chair for ASYNC'98, General Co-chair for ASYNC'07, is on the Steering Committee, and is General Chair for ASYNC'13. Dr. Beerel was a recipient of an Outstanding Teaching Award in 1997 and the Junior Research Award in 1998 and the Dean's Faculty Award for Service in 2011, all from USC's School of Engineering. He received a National Science Foundation (NSF) Career Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design and was a co-recipient of the best paper award in ASYNC'99. He was the 2008 recipient of the IEEE Region 6 Outstanding Engineer Award for significantly advancing the application of asynchronous circuits to modern VLSI chips.

Tutorials


	Low Power Design Essentials Jan Rabaey University of California at Berkeley - UCB, USA September 1^st, Tuesday, 08:40 to 10:20

	Abstract: TBD

	Ultra-Low-Voltage (ULV) IC Design: Designing for VDD below kT/q Márcio Cherem Schneider Universidade Federal de Santa Catarina - UFSC, Brazil September 1^st, Tuesday, 10:40 to 12:20

	Abstract: The main solution to reduce the energy consumption of electronic circuits is to lower the supply voltage. This tutorial presents fundamentals for the design of MOS circuits that can operate at very low supply voltages. Operation of the MOS transistor in weak inversion is highlighted owing to the limited voltages available. CMOS logic gates and the Schmitt Trigger circuit in weak inversion are analyzed. Special attention has been given to the properties of the zero-VT transistor due to its high drive capability at low voltages. Ultra-low-voltage rectifiers using diode-connected zero-VT MOSFETs operating in weak inversion are included in the presentation. Elementary amplifiers at ultra-low-voltage are reviewed. Inductive-load oscillator prototypes built in 130 nm technology demonstrate that oscillators can operate at supply voltages below the thermal voltage kT/q.

	Short Bio: Márcio Cherem Schneider received the BEngr and MSc degrees in Electrical Engineering from the Federal University of Santa Catarina (UFSC), Florianópolis, SC, Brazil, in 1975 and 1980. In 1984 he received the PhD degree in electrical engineering from the Universidade de São Paulo, Brazil, for a dissertation on bipolar transistor modeling. In 1976, he joined the Electrical Engineering Department at UFSC, where he is now a Professor. In 1995, he spent a one-year sabbatical at the Swiss Federal Institute of Technology (EPFL). In 1997 and 2001, he worked as a Visiting Associate Professor with the Department of Electrical and Computer Engineering at Texas A&M University. He has ongoing research programs in the areas of analog integrated circuits, low-voltage/low-power circuits, and MOS transistor compact modeling which have resulted in more than 60 publications in international conferences and journals. His current research interests are mainly focused on transistor modeling and transistor-level design, in particular of analog and RF circuits.

	Impact of Low Frequency Noise on the Reliability and Variability of Nano CMOS devices Jalal Jomaah Institut National Polytechnique de Grenoble - INPG, France; Lebanese University September 1^st, Tuesday, 13:40 to 15:20 CANCELLED - Due to unforeseen circumstances

	Abstract: The Modeling and characterization of low-frequency noise and noise variability in various regimes of operation are investigated for the main advanced CMOS technologies. Novel materials and innovative device architectures from 0.5µm to 20nm gate lengths are studied. The impact of gate stack, realized with ultrathin oxides, polysilicon gate and high k/metal gate is analyzed. The influence of alternative channel materials, in particular ultrathin body Silicon-On-Insulator layers, strain Si and III-V materials is addressed. The comparison of low frequency noise in advanced device architectures, including Bulk Si, Fully-Depleted SOI, FinFET, Junctionless, and Multi-gates structures, is shown. Accurate noise models, taking into account the main physical mechanisms, are proposed for all these very advanced technologies, which will be needed for the Nanoelectronics of the next decade.

	Short Bio: Jalal Jomaah was born in Lebanon. He graduated from the Institut National Polytechnique de Grenoble (Grenoble INP), France, in 1992. He received the MS and Ph.D. degrees in electronics from the same University, in 1992 and 1995, respectively. In 2002, he obtained the Habilitation diploma from the INPG authorizing him to supervise PhD. Dissertations. From 2001 to 2003, he was with the National French council of the scientific research. He joined the Laboratoire de Physique des Composants à Semiconducteurs (LPCS), INP Grenoble, in 1992, where he has been involved in research on the characterization, modeling, and simulation of fully- and partially-depleted Silicon-On-Insulator MOS transistors. He became Maître de Conférences (Associate Professor) at Grenoble INP in 1996 where he continued his research activities at IMEP (Institute of Microelectronics, Electromagnetism and Photonics, Grenoble INP/CNRS/UJF). He is now also Professor at the Lebanese University. During 2007, Dr Jomaah was received as Full Time Professor at the Department of Electrical Engineering at the United Arab Emirates University (UAEU). His main research activities were and are in the field MOS/SOI device physics, fluctuations and low and high frequencies noise and radio-frequencies applications. He is also interested by the metamaterials and electromagnetic modeling. He has supervised 15 Ph.D. and was involved in several national and international research projects on the low and high frequencies noise, reliability, modeling and characterization of SOI devices for RF applications and low-temperature physics. Dr Jomaah has co-authored over 50 publications in international scientific journals, 120 communications at international conferences (15 invited papers and review articles).

	3D ICs - Moving from Silicon to Heterogeneous Technologies Maciej Ogorzalek Jagiellonian University, Krakow, Poland September 1^st, Tuesday, 13:40 to 15:20

	Abstract: 3D integration has been proposed in recent years to overcome serious limitations in routing-connection length, power limitations and technology limits in terms of chip area and yield. The 3D technologies in silicon have reached the stage of being sufficiently ripe to move to industrial applications - hybrid memory cube, advanced FPGA chips are good examples of multilayer chips employing advanced silicon technologies. Simultaneously to development of 3D techniques one can observe extensive effort to bring into the picture new competitive devices and circuits developed using new non-silicon technologies. Various types of memories (RRAM, Spintronic), optical, chemical or bio-medical sensors, energy scavengers and energy storage elements have been developed and investigated. Possibility of integration of building blocks realized in diverse technologies is the next step we are facing, bringing new interesting concepts and new challenges. The “Much-more-then-Moore” direction brings many promises for new circuitry and new systems on chip with parameters far exceeding currently available CMOS.

	Short Bio: Maciej J. Ogorzalek is Professor and Head of the Department of Information Technologies, Jagiellonian University Krakow, Poland. He held visiting positions in Denmark, Switzerland, Germany, Spain, US, Japan, Hong Kong. In 2000/2–1 he worked at the National Microelectronic Center, Seville, Spain. In 2001 he was visiting professor at Kyoto University, in 2005 Hertie Foundation guest professor at The Goethe University Frankfurt-am-Main. 2006-2009 he held the Chair of Bio-signals and Systems, Hong Kong Polytechnic University under the Distinguished Scholars Scheme. Author of over 280 technical papers published in journals and conference proceedings, and the book Chaos and Complexity in Nonlinear Electronic Circuits (World Scientific, 1997). Dr Ogorzalek gave over 40 plenary and keynote presentations at major conferences world-wide. He serves also as Associate Editor for Journal of the Franklin Institute (1997-), International Journal of Bifurcation and Chaos (2004-), International Journal of Circuit Theory and Applications (2000-). He was the Vice-President of the Sniadecki Science Foundation (until 2005). In 2012 elected Member of Academia Europaea. He was 2008 IEEE Circuits and Systems Society President, recently elected as IEEE Division 1 Director to serve on IEEE Board of Directors 2016-2017.

	Cyber - Physical Systems: Reality, Dreams, and Fantasy Magdy A. Bayoumi University of Louisiana at Lafayette, USA September 1^st, Tuesday, 15:40 to 17:20

	Abstract: The integration of physical systems with networked sensing, computation networks, and embedded control with actuation has led to the emergence of a new generation of engineered systems, the Cyber-Physical Systems (CPS). Such systems emphasize the link between cyber space and physical environment (i.e., time, space, and energy). CPS represents the next generation of complex engineering systems. They are large scale dynamic systems that offer significant processing power while interacting across communication networks. CPS will help to solve the grand challenges of our society, such as, aging population, limited resources, sustainability, environment, mobility, security, health care, etc. Applications of CPS cover a wide band of economic, medical, and entertainment sectors. It includes; Transportation: automobiles, avionics, unmanned vehicles and smart roads; Large Scale Critical Infrastructure: bridges, mega buildings, power grid, defense systems; Health Care: medical devices, health management networks, telemedicine; Consumer Electronics: video games, audio/video processing, and mobile communication. Building Cyber-Physical Systems is not a trivial task. The difficulty arises from the existing gap in modeling and computing of the physical and cyber environments. The design process requires new theories, models, and algorithms that unify both environments in one framework. None of the current state-of-the art methods are able to overcome the challenges of developing the unified CPS design paradigm. Several of these issues will be discussed in this talk. Case studies of real world CPSs will be illustrated.

	Short Bio: Dr. Magdy A. Bayoumi is the Z.L. Loflin Eminent Scholar Endowed Chair. Professor at The Center for Advanced Computer Studies (CACS), University of Louisiana at Lafayette (UL Lafayette). He was the Director of CACS, 1997 – 2013 and Department Head of the Computer Science Department, 2000-11. Dr. Bayoumi has been a faculty member in CACS since 1985. He received B.Sc. and M.Sc. degrees in Electrical Engineering from Cairo University, Egypt; M.Sc. degree in Computer Engineering from Washington University, St. Louis; and Ph.D. degree in Electrical Engineering from the University of Windsor, Canada. Dr. Bayoumi has graduated about 60 Ph.D. and 155 Master’s students. He has published over 500 papers in related journals and conferences. He edited, co-edited and co-authored 10 books in his research interests. He has been Guest Editor (or Co-Guest Editor) of nine Special Issues in VLSI Signal Processing, Learning on Silicon, Multimedia Architecture, Digital and Computational Video, and Perception-on-a-Chip. The latest Special Issues has been on "System-on-a-Chip," IEEE Proceedings, 2006. He has given numerous invited lectures and talks nationally and internationally, and has consulted in industry. He is an IEEE fellow. Dr. Bayoumi has served in many editorial, administrative, and leadership capacities in IEEE Signal Processing Society, IEEE Computer Society, and IEEE Circuits and Systems (CAS) Society. He has been involved in many conferences, serving in different capacities. He was Associate Editor of the Transaction on Image Processing, and he is an associate editor of the Journal of VLSI Signal Processing Systems. He was an associate editor of Circuits and Devices Magazine, Transaction on VLSI Systems, Transaction on Neural Networks and Transaction on Circuits and Systems II. Dr. Bayoumi is an Associate Editor of INTEGRATION, the VLSI Journal. He was Associate Editor of the Journal of Circuits, Systems, and Computers. He was Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. Dr. Bayoumi served on the Distinguished Visitors Program for IEEE Computer Society, 1991-1994. He, also, served on Circuits and Systems Distinguished Speakers Program, 2011-2013 and 1999-2001. Dr. Bayoumi was Chair of the SPS Technical Committee on Signal Processing Systems Design and Implementation. He was the Chair and Founder of "Circuits and Systems for Communication" Technical Committee. He was one of the founders, and was Chair of VLSI Systems and Applications (VSA) Technical Committee (TC). He is a member of the Multimedia and Neural Network Technical Committees. He was on the IEEE National Committee on Engineering R&D policy, IEEE National Committee on Communication and Information Policy, and IEEE National Committee on Energy Policy. He is on the IEEE Fellow Committee and he was on the IEEE CS Fellow Committee. He is Faculty Advisor for the IEEE Computer Student Chapter at UL Lafayette, the winner of the 2002 and 2007 Outstanding Chapter Award (worldwide). He won UL Lafayette 1988 Researcher of the Year award, and 1993 Distinguished Professor award at UL Lafayette. Dr. Bayoumi is an ABET Commissioner and Team Chair. Dr. Bayoumi is the recipient of the 2009 IEEE Circuits and Systems Meritorious Service Award. He is also the recipient of the 2003 IEEE Circuits and Systems Society Education Award. He was the Vice President for Conferences, Vice President for Technical Activities, and a member of the Board of Governors and Executive Committee of CAS Society. Dr. Bayoumi served on the technology panel and advisory board of the U.S. Department of Education project, "Special Education Beyond Year 2010," 1990-1993. He was the chair of an international delegation to China, sponsored by People-to-People Ambassador, 2000. He received the French Government Fellowship, University of Paris Orsay, 2003-2005 and 2009. He received the United Nation Fellowship, Egypt, 2002-2003. He was a Visiting Professor at King Saud University.

	Low Loss, High Isolation, Linear RF Switch Design in SOI Peter H. Popplewell Skyworks Solutions, Canada September 1^st, Tuesday, 15:40 to 17:20 CANCELLED - Due to unforeseen circumstances

	Abstract: The tremendous popularity in recent years of wireless connected devices, especially those containing multi-band capable radios, or those making use of antenna tuning or antenna diversity has led to widespread demand of high quality RF switch circuits. Requirements range from simple single-pole double-throw (SP2T) with single-bit control interfaces, to upwards of 20-throw switches with mipi digital interfaces and on-die logic decoding. Insertion loss requirements below 0.5dB at RF frequencies are common, with isolation between RF ports of 30 dB or better being achievable. Cellular applications can require switches tolerant of over +35 dBm of signal power, often with additional robustness required to handle VSWR conditions under mismatch. This tutorial discusses the suitability of SOI technology at addressing many of these challenging requirements. SOI has excellent RF properties, high voltage tolerance for stacked devices, and the ability to integrate common CMOS circuits for the purpose of supporting and optimizing the RF functions of a switch die. Switch biasing schemes and their tradeoffs are discussed, along with the fundamentals of RF switch design in SOI, designing for high voltage tolerance, low vs. high band insertion loss, optimal isolation, ESD protection, and linearity. Analog support circuits such as negative-voltage generators are introduced, as well as practical layout strategies for minimizing noise and switch loss. The Ron/Coff figure of merit is discussed, as well as flip-chip, WLCSP and wire bonded packaging options and their associated effects on performance.

	Short Bio: Received his B.Eng. degree in Electrical Engineering in 2002, his M.A.Sc. degree in 2004, and his Ph.D. degree in 2010 from Carleton University, Ottawa, Canada. He currently manages an RF/Analog IC design team at Skyworks Solutions’ Ottawa design center. Peter Joined Skyworks in 2008 and has co-developed numerous cellular and WiFi-band RF switches which are now in production - primarily using SOI and CMOS technologies. From 2004 to 2008 he worked for Kleer Semiconductor designing CMOS RFICs for use in wireless audio devices such as wireless earphones for iPods, and wireless home stereo speakers. Peter’s Ph.D. research focused on low-power CMOS design techniques facilitating completely integrated medical sensors and RFID tag devices that use integrated antennas and power sources. He Holds 4 patents and has been published in 2 IEEE journals and 9 IEEE conference proceedings.

Invited Talks


	Frame Free Vision Teresa Serrano-Gotarredona IMSECNM-CSIC, Sevilla; University of Sevilla, Spain September 2^nd, Wednesday, 13:20 to 14:00

	Abstract: State of the art in artificial vision is based on video streams, by capturing sequences of images at a given "frame rate" and processing them frame after frame by computational algorithms. On the other hand, biological vision is frame-free: neither the eyes nor the brain have a clue of what a video frame is. In biology, retina cells (pixels) send electric spikes (also called "events") asynchronously to the brain through the optical nerve fibers. Cells in the brain process these spikes through complex hierarchical structures to achieve, for example, shape size and pose invariant object recognition. There are no frames, but just a continuous flow of spikes/events from the retina through the cortical brain structures. Recently, several groups worldwide are developing bioinspired vision sensors and processors where the visual information is not represented as a sequence of frames but as a continuous flow of events or spikes. This asynchronous frame-free sensing and processing paradigm is also called "event-driven" (as opposed to "frame-driven"). New event-driven vision sensor chips sensitive to temporal changes in the visual scene (also called Dynamic Vision Sensor or DVS) together with event-driven convolution module arrays implemented on chip or using high-end FPGAs will be presented. Finally examples on how by modularly interconnecting event-driven sensors and processors complex real-time recognition systems can be assembled will be shown.

	Short Bio: Teresa Serrano-Gotarredona received the B.S. degree in electronics physics and the Ph.D degree in VLSI neural categorizers from the University of Seville, Sevilla, Spain in 1992 and 1996, respectively. She got the M.Sc. degree from the Department of Electrical and Computer Engineering of the Johns Hopkins University in 1997. She was assistant professor in the Electronics and Electromagnetism Department of the University of Sevilla from September 1998 until June 2000. Since September 2000, she has been a Tenured Scientist at the National Microelectronics Center, (IMSECNM-CSIC) Sevilla, Spain, and in July 2008, she was promoted to Tenured Researcher. Since January 2006, she has been also part-time professor at the University of Sevilla. Her research interests include analog circuit design of linear and nonlinear circuits, VLSI neural based pattern recognition systems, VLSI implementations of neural computing and sensory systems, transistor parameter mismatch characterization, address-event-representation VLSI, nanoscale memristor-type AER, and real-time vision sensing and processing chips. Dr. Serrano-Gotarredona was co-recipient of the 1995-96 IEEE Transactions on VLSI Systems Best Paper Award for the paper "A Real-Time Clustering Microchip Neural Engine". She has also been co-recipient of the 2000 IEEE Transactions on Circuits and Systems Darlington Award for the paper "A General Translinear Principle for Subthreshold MOS Transistors". She is co-author of the book "Adaptive Resonance Theory Microchips ". She is currently chair of the Sensory Systems Technical Committee of the IEEE Circuits and Systems Society and chair of the IEEE Circuits and Systems Spain Chapter. She was academic editor of the PLoSOne from May 2008 until October 2013, and she serves as associate editor of the IEEE Transactions on Circuits and Systems-I, regular papers since January 2012 and the IEEE Transactions on Circuits and Systems-II, express briefs since January 2014.

	System-Level Design of Heterogeneous System-on-Chip Architectures Luca Carloni Columbia University, USA September 3^rd, Thursday, 13:20 to 14:00

	Abstract: The heterogeneous multi-core system-on-chip, which combines programmable processors and specialized hardware accelerators, is emerging as a dominant platform architecture across many computing domains, from mobile devices to data centers. Accelerators offer an effective design solution in the face of tight power budgets because they provide energy-efficient performance for critical computation kernels and are activated via software only when needed. The presence of many accelerators, however, increases design heterogeneity, which in turn exacerbates system complexity and prolongs design time. To address these challenges I present a design methodology that raises the level of abstraction to the system level, simplifies the integration of heterogeneous components, and leverages recent results on supervised design-space exploration for component reuse. I illustrate the effectiveness of this approach by describing its application to the design of complex system-on-chip prototypes with both FPGA and ASIC technologies.

	Short Bio: Luca Carloni is an Associate Professor of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His research interests include methodologies and tools for multi-core system-on-chip platforms with emphasis on system-level design and intellectual property reuse, design and optimization of networks-on-chip, and distributed embedded systems. He coauthored over one hundred refereed papers and is the holder of two patents. Luca received the Faculty Early Career Development (CAREER) Award from the National Science Foundation in 2006, was selected as an Alfred P. Sloan Research Fellow in 2008, and received the ONR Young Investigator Award and the IEEE CEDA Early Career Award in 2010 and 2012, respectively. In 2013 Luca served as general chair of Embedded Systems Week (ESWeek), the premier event covering all aspects of embedded systems and software.

	Rethinking “Things” Design - the Missing Technology Link in the Internet of Things Massimo Alioto National Univ. of Singapore September 4^th, Friday, 13:20 to 14:00

	Abstract: The Internet of Things (IoT) has now become a main driver in research and next-generation technology development, and is expected to foster the growth of the semiconductor industry in the next decade or more, once the wave of mobile platforms reaches its peak. In spite of daily announcements of new industrial projects in the IoT domain, the physical nodes that gather sensed data (the “things”) are still technologically immature, and well behind the rest of the IoT infrastructure. This lag has been determined by several daunting challenges in terms of energy efficiency and security under tight cost constraints, as well as a rigid view on the quality of service provided by IoT nodes. Energy efficiency is indeed synonym for node availability and size, whereas cheap chip-level security is a necessary premise to build adequate trust in the minds of potential adopters. This keynote speech addresses these fundamental issues and sketches a map to move towards the true realization of the physical layer of IoT, and ultimately enable IoT nodes with extreme energy efficiency and unceasing security, in both space (across nodes) and time (in each node). The scalable quality of service in IoT nodes is shown to be a key ingredient to relax the critical design tradeoffs, and generalize the well-known concept of “QoS” that is ubiquitously applied in the Internet of today. A perspective is finally given on the future role of technology and EDA industry in the IoT arena, based on the natural bottom-up (business) pressure that has made the Internet possible in the past. And will make the Internet of Things real in the future. .

	Short Bio: Massimo Alioto is Associate Professor at the ECE Department of the National University of Singapore, where he leads the Integrated Circuits and Embedded Systems area (80+ people) and the Green IC group. Previously, he was Visiting Scientist at Intel Labs – CRL (2013), Visiting Professor at the University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL – Lausanne (2007), and Associate Professor at the University of Siena. He is (co)author of 200+ publications on journals (75+, mostly IEEE Transactions) and conference proceedings, and two books with Springer. His primary research interests include ultra-low power VLSI circuits, self-powered/wireless nodes, near-threshold circuits for green computing, energy-quality scalable VLSI circuits, circuits for HW-level security and for emerging technologies. He is currently Associate Editor in Chief of the IEEE Transactions on VLSI Systems. He also serves or has served as Associate Editor of several IEEE and ACM journals. He served as Guest Editor of various journal special issues (e.g., “Ultra-Low Voltage Circuits and Systems for Green Computing” on IEEE TCAS-II). He is/was Technical Program Chair of several IEEE conferences (ICECS, VARI, NEWCAS, ICM), and Track Chair in several others (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). In the last five years, he has given 50+ invited talks in top universities and leading semiconductor companies. He is/was Distinguished Lecturer (2009-2010) and member of the Board of Governors of the IEEE Circuits and Systems Society (2015-2016).