Consumers demands for societal challenges in fields like healthcare,
mobile transportation, autonomous driving, smart energy, smart cities and
Internet of Things are driving the revolution and innovation in micro- and nano-
electronics.  Things, homes and cities are getting smart and interact with each
other, posing challenges on the availability of dedicated sensors, detectors,
monitors, diagnostic devices, the handling of big data and high performing
communication tools. The implementation of 5G networks with high data rates
(10 Gbps), large bandwidth (1 GHz to mmwave) and low latencies (< 1ms) are
of key importance.

CMOS devices, driven by minimum device geometry, performance
enhancement, cost issues and low power consumption, are achieved by using
optimizing process modules, introducing new materials and implementing novel
device concepts. Advanced device structures including FinFETs, TFETs, Gate-
All-Around (GAA) and horizontal and vertical nanowires (NWs) are required for
both logic and analog/RF building blocks to enable the envisaged System-on-
Chip (SoC) applications. Heterogenous integration of Ge and III-V technologies
on a silicon platform is receiving a lot of attention. Beside 3D stacking using
Through -Silicon-Via (TSV) for wafer-to-wafer bonding, very promising results
are obtained for monolithic sequential 3D processing.

This presentation will review major trends in CMOS process integration
and discusses technological challenges of some key process modules and
device structures.

Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium”, “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. Two books are translated in Chinese. He (co)authored 14 book chapters, over 1100 conference presentations and more than 1300 technical and peer-reviewed papers.

He is editor/co-editor of 60 Conference Proceedings. Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. Within the Electrochemical Society, he was Chair of the Electronics & Photonics Division (2001-2003). In 2004, he received the Electronics & Photonics Division Award.

Spintronics technology provides an exciting platform for implementing computational structures, and recent work has demonstrated the potential for leveraging its nonvolatility properties to build energy-efficiency systems. This talk presents a view of the state of the art in this field, as well as a view of cutting-edge research directions. We will present results from our collaborative efforts involving physicists, material scientists, circuit designers, and architects, which have led to the development of novel device structures, circuits, and memory arrays. Together, these help construct viable pathways for building spin-based structures for computation, memory, and in-memory computation, including for AI applications. Spin-based memories are nonvolatile and are conventionally based on arrays of magnetic tunneling junctions (MTJs).

The talk will first show the current state of technology for building spin-based memories, and then present directions for next-generation improvements in spintronic memory technologies. We will then present spin-based structures that have also been shown to be highly efficient for logic applications in specific scenarios, such as those that require nonvolatility or are used for error resilient applications. Finally, we will show methods for building spin-based compute-in-memory structures that are greatly advantageous for data-intensive applications, and demonstrate the efficiencies that can be achieved by this model for a neuromorphic application.

Sachin Sapatnekar is an IEEE Fellow, full professor at Univ. of Minnesota, and a CEDA Distinguished Lecturer. He received the B. Tech. degree from the Indian Inst. of Technology, Bombay, in 1987, the M.Sc. from Syracuse University in 1989, and the Ph. D. degree from the University of Illinois at Urbana-Champaign in 1992. He worked at Texas Instruments during the summer of 1990, and at Intel Corporation during the summer of 1997.

He was an Assistant Professor in the Department of Electrical and Computer Engineering at Iowa State University from 1992 to 1997. He is currently a Professor in the Department of Electrical and Computer Engineering at the University of Minnesota, where he holds the Robert and Marjorie Henle chair and the Distinguished McKnight University Professorship. His current research interests lie in developing efficient techniques for computer-aided design of integrated circuits and are primarily centered around physical design, timing and simulation issues, and optimization algorithms.He has served on the editorial boards of several IEEE journals, including as Editor-in-Chief of the IEEE Transactions on CAD. He was a Technical Program Co-chair in 2006 and 2007 for the Design Automation Conference (DAC), and the General Chair in 2010.

He has also been the Technical Program Chair and General Chair for the International Symposium on Physical Design (ISPD) and the Tau workshop, and Program Chair for the International Conference on VLSI Design in India. He is a recipient of the NSF Career Award, the SRC Technical Excellence Award, the SIA University Researcher Award, Best Paper Awards at the DAC’97, ICCD’98, DAC’01 DAC’03, ISPD’09, ISQED’10, and ASYNC’16 conferences, a Best Poster Award at IRPS’12, and the ICCAD Ten-Year Retrospective Most Influential Paper Award in 2013 and 2016. He has been a Fulbright Senior Researcher at Universitat Politècnica de Catalunya in Barcelona in 2013, and a DJ Gandhi Visiting Professor at the Indian Institute of Technology, Bombay in 2014. He is a Fellow of the IEEE (2003) and the ACM (2016).

Jan holds the Donald O. Pederson Distinguished Professorship at the University of California at Berkeley. He is a founding director of the Berkeley Wireless Research Center (BWRC) and the Berkeley Ubiquitous SwarmLab, and has been the the Electrical Engineering Division Chair at Berkeley twice. Prof. Rabaey has made high-impact contributions to a number of fields, including advanced wireless systems, low power integrated circuits, sensor networks, and ubiquitous computing. His current interests include the conception of the next-generation integrated wireless systems over a broad range of applications, as well as exploring the interaction between the cyber and the biological world. He is the recipient of major awards, amongst which the IEEE Mac Van Valkenburg Award, the European Design Automation Association (EDAA) Lifetime Achievement award, and the Semiconductor Industry Association (SIA) University Researcher Award. He is an IEEE Fellow, a member of the Royal Flemish Academy of Sciences and Arts of Belgium, and has received honoray doctorates from Lund (Sweden), Antwerp (Belgium) and Tampere (Finland). He has been involved in a broad variety of start-up ventures.

With the world around us rapidly becoming smarter, an extremely relevant question is how ‘we humans’ are going to cope with this onslaught of information. One possible answer is for us to use similar technologies to evolve ourselves, and to equip us with the necessary tools to interact with and to become an essential part of the smart world.

Various wearable devices have been or are being developed to do just that. However, their potential to create a whole new set of human experiences is still largely unexplored. To be effective, functionality cannot be centralized and needs to be distributed to capture the right information at the right place. This requires a human intranet, a platform that allows multiple distributed input/output and information processing functions to coalesce and form a single application. In this presentation, we focus on the computational aspects of such an intranet, tasks that are complicated by the extreme energy and form-factor limitations imposed on the wearable (or implanted) devices. An important aspect is that the human intranet should not only be able to learn from experience, but capable of dealing with changes in both the environment and in itself. Moreover, it should be able to do so on a continuous base. Dealing with novelty and unexpected situations is something we humans do well. Computational models, architectures and circuits that enable such capabilities at ultra-low energy and small form factor are hence needed. A glimpse of what may be possible will be presented.