Technical Program
  Monday, August 31th Tuesday, September 1st Wednesday, September 2nd Thursday, September 3rd
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8:00-8:30 Registration      
8:30-9:00 invited 1 Invited Michel M. Maharbiz     SBµ 7 MGates I SBCCI 6 
SForum 5 SBCCI 7 
SBµ 11 FLASH + Posters SBCCI 11 
II Emicro
Invited Talk
9:00-9:30 Tutorial 01 - Michel M. Maharbiz SBµ 1 OPTO I SBCCI 1 
SForum 1
SForum 3
9:30-10:00 CI BRASIL
10:00-10:30 FARNELL NEWARK MOSIS   II Emicro
Analog Design
II Emicro
Embedded System Design
10:30-11:00 Coffee Break Coffee Break Coffee Break posters up Coffee Break
11:00-11:30 Tutorial 02  Vasileska Tutorial 03  Mohamed Sawan invited 2 SBCCI 2 

SForum 2
SForum 4

invited 3 invited 6 SBCCI 8 
SForum 6 SBµ 9 MGates II Noc-based Design HDTV Hardware Design
11:30-12:00 SBµ 2 MODEL I SBµ 3 OPTO II SBµ 8 Devices I
12:30-14:00 Lunch Lunch Lunch Lunch
14:00-14:30 Tutorial 04 Parneix Tutorial 05 Calvin Plett SBµ 4 OPTO III Invited Mohamed Sawan LASCUG 2009 invited 4 SBµ 10 MODEL II SBCCI 9 
SForum 7 invited 7 SBCCI 12 RF (2) SForum 8 SBCCI 13 RELIABILITY
14:30-15:00 SBCCI 3 DSP (1) SBµ 5 Process I SBµ 12 Devices II
Coffee Break
16:00-16:30 Tutorial 06 Kazmiruk Tutorial 07  Andre Reis Coffee Break Coffee Break Coffee Break
16:30-17:00 invited 5 Invited Calvin Plett SBCCI 5 TEST Policy Panel: Microelectronics in Brazil (in portuguese)   invited 8 SBCCI 14 
SForum 9 SBµ 14 MODEL III
17:00-17:30 SBµ 6 Process II SBCCI 4 
RF (1)
SBµ 13 Devices III
17:30-18:00   Technical Panel
18:00-18:30 NAMITEC
18:30-19:00   CECCI Meeting (in portuguese)       SBµ Meeting (in portuguese) Closing session - Best papers  
19:30-20:00 Official Opening
20:00-20:30 Cocktail          
20-30-22:00 Conference Dinner


SBCCI'09 Detailed Program (pdf version)

SESSION 1 (Tuesday 9h00 – 10h30): Embedded Systems
Chair: Edna Barros, UFPE

Low-power inter-core communication through cache configurability in embedded multiprocessors
Chenjie Yu and Peter Petrov

Exploiting the Model Driven Engineering Approach to Improve Design Space Exploration of Embedded System
Marcio F. da S. Oliveira, Ronaldo Rodrigues Ferreira, Francisco Assis do Nascimento, Franz Josef Rammig and Flavio Rech Wagner

A Hybrid Methodology for Tuning Two-Level Cache Hierarchy considering Energy and Performance
Abel Silva-Filho and Cristiano Araújo

Design of an Embedded System for the Proactive Maintenance of Electrical Valves
Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Renato Ventura Bayan Henriques and Marcelo Lubaszewski

SESSION 2 (Tuesday 11h00 – 12h30): Analog Design (1)
Chair: Wilhelmus Van Noije, USP

Determination of Distortion in Analog Multiplier Circuits by Two-Dimensional Integral Nonlinear Function
Luciano Abreu de Lacerda, Edson Pinto Santana, Cleber Vinicius Ribeiro de Almeida and Ana Isabela Araújo Cunha

A Fast-Response Charge-Pump Gate Driver Applied to Linear Regulation
Andre Mansano, Jader A. De Lima and Jacobus Swart

A self-protected integrated switch in a HV technology
Matias Miguez, Alfredo Arnaud and Joel Gak

SESSION 3 (Tuesday 14h30 – 16h00): DSP and Arithmetic Circuits (1)
Chair: Volnei A. Pedroni, UTFPR

High Performance Motion Estimation Architecture Using Efficient Adder-Compressors.
André Silva, Marcelo Porto, Eduardo Costa and Sergio Bampi

Design of a Low Power MPEG-1 Motion Vector Reconstructor
Marco A. Ochoa-Montiel, Bashir M. Al-Hashimi and Peter Kollig

Dedicated Architecture for the Transforms and Quantization Loop of the H.264/AVC Intra Prediction
Robson Dornelles, Felipe Sampaio, Daniel Palomino and Luciano Agostini

SESSION 4 (Tuesday 17h00 – 18h30): RF Design (1)
Chair: Fernando Rangel, UFRN

A Merged RF CMOS LNA-Mixer Design using Geometric Programming
Sergio Chaparro, Armando Ayala Pabón, Elkim Roa and Wilhelmus Van Noije

Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies
Rafaella Fiorelli and Fernando Silveira

A Novel Delta Sigma Built-In-Current-Sensor as a Signal Strength Indicator for RF Transceiver Reconfiguration
Laurent Leyssenne, Eric Kerhervé, Yann Deval and Didier Belot

SESSION 5 (Tuesday 16h30 – 18h00): Test
Chair: José Luís Güntzel, UFSC

A Parameter-Domain-based Methodology to Enhance Efficiency in Testbenches with Random Stimulation
Carlos Ivan Castro Marquez, Marius Strum and Wang Jiang Chau

Testing Configurable Quaternary Logic Blocks
Érika Cota, Luigi Carro, Felipe Pinto, Marcelo Lubaszewski and Ricardo Reis

A Logic Built-in Self-test architecture that reuses manufacturing compressed scan test patterns
Diogo Alves and Edna Barros

Simultaneous Impulse Stimulation and Response Sampling Technique for Built-In Self Test of On-Chip Linear Analog Circuits
Wimol San-um and Tachibana Masayoshi

NAMITEC - National Institute of Science and Technology
Speaker: Jacobus W. Swart

SESSION 6 (Wednesday 08h30 – 10h00): Network-on-Chip
Chair: Ricardo Jacobi, UnB

A Path-Load Based Adaptive Routing Algorithm for Networks-on-Chip
Leonel Tedesco, Fabien Clermidy and Fernando Moraes

Using NoC Routers as Processing Elements
Silvio Fernandes, Bruno Cruz and Ivan Saraiva

Adding Mechanisms for QoS to a Network-on-Chip.
Marcelo Daniel Berejuck and Cesar Albenes Zeferino

Improving Reliability in NoCs with Reconfigurable Router
Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Kastensmidt, Marcio Kreutz and Altamiro Susin

MOSIS: Low Volume, Low Cost IC Fabrication via MOSIS
Speaker: Hudson J. Mota de Alcântara
Biography: Hudson has worked in the Semiconductor industry for almost 20 years now. Starting as an ASIC designer for AT&T Bell Lab, he also worked for University of Pennsylvania, and Vitesse Semiconductor Corp., before joining USC/ISI/MOSIS, where he has been for the last eight years. He has an engineering degree from UFRJ, and a masters degree from UNICAMP.

SESSION 7 (Wednesday 08h30 – 10h30): Analog Design (2)
Chair: Carlos Galup, UFSC

A Compact Low-Distortion Low-Power Instrumentation Amplifier
Jader A. De Lima

A Low-Voltage Bandgap Reference Source Based on the Current-Mode Technique
Juan José Carrillo, Elkim Roa, José Vieira and Wilhelmus Van Noije

Zero Quiescent Current Startup Circuit with Automatic Turning-off for Low Power Current and Voltage Reference
Alfredo Olmos, André Vilas Boas, Jefferson Soldera and André Mansano

Design and Characterization of a 0.35 micron CMOS Voltage-to-Current Converter
Genval Mariano de Araujo, Heider Marconi G Madureira, Jose Camargo da Costa

SESSION 8 (Wednesday 11h00 – 12h30): Power Dissipation
Chair: Diogenes C. da Silva Jr.,UFMG

A High Abstraction, High Accuracy Power Estimation Model forNetworks-on-Chip
Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, CezarReinbrecht, Thiago Raupp, Fernando Moraes

DRAM Power Management and Energy Consumption: a Critical Assessment
Daniel Schmidt and Norbert Wehn

On the Energy-Efficiency of Software Transactional Memory
Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte and Rodolfo Azevedo

SESSION 9 (Wednesday 14h00 – 15h30): Digital Design
Chair: Altamiro Susin, UFRGS

System concept for a FPGA based real-time capable automotive ECU restbus simulation system
Oliver Sander, Christoph Roth, Vitali Stuckert and Jürgen Becker

ASIC Design of a Novel High Performance Neuroprocessor Architecture for Multi Layered Perceptron Networks
Igor Dantas dos Santos Miranda

A Parametric Expression-Grain Reconfigurable Architecture
Juan eusse, Michael Hubner and Ricardo Jacobi

Improved Placement for Hierarchical FPGAs Exploiting Local Interconnect Resources
Valerij Matrose and Carsten Gremzow

SESSION 10 (Wednesday 14h00 – 16h00): Sensor Design
Chair: Marcelo Antonio Pavanello, FEI

Pipelined Successive Approximation Conversion (PSAC) with Error Correction for a CMOS Ophthalmic Sensor
Frank Sill and Davies William de Lima Monteiro

Floating Gate MOSFET Circuit Design for its use in a Monolithic MEMS Gas Sensor.
Mario Alfredo Reyes-Barranca, Salvador Mendoza-Acevedo, Luis Martin Flores-Nava, Alejandro Avila-Garcia and Jose Luis Gonzalez-Vidal

CI Brasil: IC-Brazil Program and Current Design Houses
Speaker: Jacobus W. Swart (IC Brazil Coordinator)

SESSION 11 (Thursday 08h30 – 10h30): DSP and Arithmetic Circuits (2)
Chair: Fernando Gehm Moraes, PUCRS

Parameterizable Floating-point Library for Arithmetic Operations in FPGAs
Diego F. Sanchez, Daniel M. Muñoz, Carlos H. Llanos and Mauricio Ayala-Rincón

High Throughput and Low Cost Architecture for H.264/AVC Context Adaptive Variable Length Decoder Targeting HDTV
Thaísa Silva, Fabio Pereira, Luciano Agostini, Altamiro Susin and Sergio Bampi

Architecture for Dense Matrix Multiplication on a High-Performance Reconfigurable System
Viviane Souza, Victor Medeiros, Derci Lima, Abner Barros, Paulo Sérgio Nascimento and Manoel Lima

Design of Low Complexity Digital FIR Filters
Levent Aksoy, Diego Jaccottet and Eduardo Costa

SESSION 12 (Thursday 14h00 – 16h00): RF Design (2)
Chair: Calvin Plett, Carleton University

Voltage Controlled Delay Line With Phase Quadrature Outputs For [0.9-4] GHZ F-Dll Dedicated To Zero-If Multi-Standard Lo
Cedric Majek, Yann Deval, Hervé Lapuyade and Jean-Baptiste Bégueret

High IIP2 down-converter for homdyne receivers
Antônio Felipe Silva and Fernando Rangel de Sousa

Comparision of Small Cross Inductors and Rectangular Inductors Designed in 0.3µm CMOS Technology
Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón and Andrés Farfán-Peláez

CMOS 2.45GHz RF Power Amplifier for RFID Reader
Md. Jasim Uddin, Mamun Bin Ibne Reaz, Muhammad Ibn Ibrahimy, Anis Nurashikin Nordin, Muhammad Asraful Hasan and Mohd Alauddin Mohd Ali

SESSION 13 (Thursday 14h00 – 16h00): Reliability
Chair: Sergio Bampi, UFRGS

Reliability Aware Yield Improvement Technique for Nanotechnology Based Circuits
Costas Argyrides, Carlos Lisboa and Luigi Carro

Protecting Digital Circuits Against Hold Time Violation Due to Process Variability
Gustavo Neuberger, Gilson Wirth and Ricardo Reis

Twin Gates – Improved Reliability concerning Gate Oxide Breakdown by Redundancy
Hagen Saemrow, Claas Cornelius, Frank Sill, Andreas Tockhorn and Dirk Timmermann

SESSION 14 (Thursday 16h30 – 18h30): Verification
Chair: Carlos Arthur Lang Lisbôa, UFRGS

A MDE Approach to the Formal Verification of UML based Embedded Systems Specifications
Francisco Assis Moreira Nascimento, Marcio Ferreira da Silva Oliveira and Flávio Rech Wagner

Function Verification of Power Gate Design in SystemC RTL
George Silveira, Alisson Vasconcelos Brito and Elmar Melcher

Design Validation of Multithreaded Architectures Based on Concurrent Threads Cultivation
Danilo Ravotto, Ernesto Sanchez, Matteo Sonza Reorda and Giovanni Squillero

An Early Real-Time Checker for Retargetable Compile-Time Analysis
Emilio Wuerges, Luiz C. V. Santos, Olinto Furtado and Sandro Rigo