VOLUME 3 – NÚMERO 1 – ANO 2013
Workshop on Circuits and System Design
ARTIGOS
Design of a Wideband LNA for Human Body Communication
Maicon D. Pereira and Fernando Rangel de Sousa
A Low-Power, 10-bit, 185 kSPS CMOS SAR Analog-to-Digital
Converter
William Prodanov, Lucas de Mello Kindermann and Paulo Augusto Dal Fabbro
Bulk Biased RF Energy Harvesting Dedicated to 900MHz/2.4GHz ISM
Bands
Dean Karolak, Thierry Taris, Yann Deval, Jean-Baptiste Bégueret and André Mariano
A Fully Integrated, Programmable, 0.1–1.5A, Li-Ion CMOS Battery
Charger
Daniel Pasti Mioni, Tatiana Dias Martins de Carvalho, Juan Carlos Mateus Ardila and Murilo Pilon Pessatti
Design and Implementation of a WISHBONE-compatible Low-Noise Arbitrary
Waveform Generator with DAC compensation
Cecil Melo and Ricardo E. de Souza
Design and FPGA Prototyping of a DVB-S2 Receiver: Towards a VLSI
Implementation in CMOS
Eduardo Rodrigues de Lima, Augusto Queiroz, Gabriel Santos da Silva, Felipe Andres Manrique Erazo and José
Eduardo Bertuzzo
MPSoC with IPNoSys as Processing Element
Andre Luiz Viana and Sílvio Roberto Fernandes
Interactive Power and Area Reduction Applied to an UHF RFID Digital
Block
Gabriel Tadeo, Fernando Luis Herrmann, Júlio Leão, Gerald Garcia and João Baptista dos Santos Martins
Full Design of an Electrochemical Impedance Spectroscopy
Sensor
Erasmo Chiappetta Filho, Luiz Eduardo Bento Ribeiro and Fabiano Fruett
A 0.18 µm Variable Gain Transimpedance Amplifier for 2.4 GHz IEEE
802.15.4 Direct Conversion Receiver
Germán Fierro, Pedro Toledo, Sandro Ferreira and Eric Fabris
Variability Analysis of the CMOS OTA Performance Designed by an
Evolutionary System
Rodrigo Alves de Lima Moreto, Gabriel Augusto da Silva, Carlos Eduardo Thomaz and Salvador Pinillos Gimenez
Fully Automated, Low Cost, Bench-Testing Solution for Analog/Mixed-Signal
Integrated Circuits
Erasmo Chiappetta, Sergio Rueda, Murillo Franco, Julian Jenkins, Flavilene Souza and José Bertuzzo
Exploring EPC Gen-2 clock generation with self-calibrating
oscillator
Lucas Teixeira and Gustavo Fernando Dessbesell
A pipelined semi-parallel LDPC Decoder architecture for
DVB-S2
Denise Costa Alves, Eduardo Rodrigues Lima and José Eduardo Bertuzzo
Evaluating the Costs of Communication Services in a Network Interface for
a Network-on-Chip
Douglas Melo, Michelle Wangham and Cesar Zeferino
A Synthesizable Serial-in Syndrome Calculator for DVB-S2 BCH
Decoding
Cesar G. Chaves, Eduardo R. Lima, Jacqueline G. Mertes and Jose E. Bertuzzo