ABSTRACT: The growth in the number of connected devices towards the trillion scale will be fundamentally impeded by batteries as a conventional source of energy, as their deployment in the trillions poses clear economic, logistical and environmental sustainability challenges.
This keynote introduces the key ideas and their silicon demonstrations to enable a new breed of always-on silicon systems from sensing, to computing and wireless communications with no battery inside (or any other energy storage). Sensor interfaces, processors and wireless transceivers fitting existing infrastructure (e.g., WiFi) with power reductions by orders of magnitude are discussed and exemplified by recent silicon demonstrations, and their system integration.
Ultimately, the technological pathway discussed in this keynote supports sustainable growth of applications leveraging large-scale deployments of silicon systems, making our planet smarter. And greener too.

BIO: Massimo Alioto (Fellow, IEEE) is currently a Professor with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he leads the Green IC Group, and also the Director of the Integrated Circuits and Embedded Systems Area and the FD-FAbrICS research center on intelligent&connected systems. Previously, he held positions at the University of Siena (Italy), Intel Labs (USA), University of Michigan, Ann Arbor (USA), University of California at Berkeley (USA), and EPFL (Switzerland).
He has authored or coauthored about 350 publications on journals and conference proceedings. He is the coauthor of five books printed by Springer, including the popular Enabling the Internet of Things—From Circuits to Systems (Springer, 2017). His research interests include self-powered integrated systems, intelligent and connected systems, widely energy-scalable integrated systems, data-driven systems for edge computing, hardware security, and emerging technologies.
Prof. Alioto is the Editor-in-Chief of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and is/was a Distinguished Lecturer of the IEEE Solid-State Circuits and Circuits and Systems Society, for which he was also a member of the Board of Governors. He is/was the Technical Program Chair (e.g., ISCAS 2023, SOCC, ICECS, and NEWCAS) in numerous conferences, and is in the IEEE “Digital Architectures and Systems” ISSCC Subcommittee and the IEEE ASSCC TPC. He has served as a Guest Editor for several IEEE journal special issues (e.g., JSSC, TCAS-I, TCAS-II, JETCAS) and an Associate Editor for a number of IEEE and ACM journals. He was the Deputy Editor-in-Chief of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto is an IEEE Fellow.

Painel 1: Desenvolvimento de Talentos para a Indústria de Semicondutores
Organizador/Moderador: Marcelo Lubaszewski, UFRGS
Painelistas:
Linnyer Beatrys Ruiz Aylon, Projeto Manná – UEM
Alcides S. Costa, InPlace Design Automation
Rodrigo Alves de Lima Moreto, MTG2i Solutions Ltda

ABSTRACT: Presence of non-idealities and defects in VLSI technologies is an immutable reality, which, however, is often overlooked by device engineers, researchers, technologists, and designers alike. We argue that in fact VLSI reliability “makes or breaks” any new technology. Superficial device reliability optimization is possible using phenomenological observations only, but we argue that solid physical foundations and thorough understanding of the underlying degradation mechanisms are essential both for truly dependable lifetime projections and for novel device pathfinding. Based on the detailed investigation of gate oxide defects, our “defect engineering” approach enables, among other things, optimization paths for SiGe channel devices and new oxidation techniques for advanced gate-all-around architectures, such as nanosheets and forksheets. In deeply scaled devices, degradation mechanisms can be decomposed down to individual defects, with each defect measured separately and its properties described down to single Kelvin temperatures using quantum mechanics. Such knowledge then allows us e.g. to model the degradation statistics of deeply-scaled devices and to predict the likelihoods of their failure. Robust degradation models enable us to project wider safe operating areas, which in turn allow to design better-performing circuitry at a given technology node and thus limited costs. Moreover, the ubiquitous presence of defects can be in fact embraced and the in-depth knowledge of defect properties can be used to our advantage to design new devices and applications, ranging from memory to physically unclonable functions and tamper-aware aging monitors.

BIO: Dr. Ben Kaczer is a Scientific Director in the FEOL reliability group at imec. Dr. Kaczer received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively. For his Ph.D. research on the ballistic-electron emission microscopy of SiO2 and SiC films he received the OSU Presidential Fellowship and support from Texas Instruments, Inc. In 1998 he joined the reliability group of imec, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge, SiGe, III-V, and MIM devices.
He has co-authored more than 500 journal and conference papers and 4 patent groups related to device and circuit reliability, presented a number of invited papers and tutorials, and received 6 IEEE International Reliability Physics Symposium (IRPS) Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. In 2019 he was historically the most cited author of IRPS. His h-index on Google Scholar is 62.
Dr. Kaczer has served twice as the chair of the Characterization, Reliability and Yield subcommittee of the International Electron Device Meeting (IEDM; 2007 and 2015) and as a member of various subcommittees of the IRPS (2002—2016) and is currently serving as a member of IRPS management committee (2018—). He was the General Chair of the Semiconductor Interfaces Specialists Conference (SISC; 2006) and continues to act as the conference secretary (2007—). He co-organized the INFOS conference (2005), and served on the INFOS, WoDiM, IPFA, and ICICDT conference committees. He has served on the Editorial Board of IEEE journal of Transaction of Electron Devices for three terms (2011—2019).

The Brazilian Semiconductor Industry: New Opportunities?
Organizer: Marcelo Lubaszewski, UFRGS
Moderator: Arthur Liraneto, CESAR
Panelists:
Murilo Pessatti, Chipus Microelectronics
Julio Leão da Silva Jr., Ensilica
Júlio de Oliveira, Idea! Electronic Systems

ABSTRACT: TBD

BIO: Dr. Iole Moccagatta is a Principal Engineer at Intel working on HW Multimedia IPs that are integrated on Intel platforms. Prior to Intel she hold the position of Senior Video Architect at NVIDIA, and that of Science Director at IMEC, Belgium. Dr. Moccagatta has been a very active member of MPEG, ITU-T, and JPEG, where she has represented US interests and companies and made a large number of technical contributions. A number of those have been included in MPEG and JPEG standards. She is currently Co-chair of the MPEG/ITU-T Joint Video Experts Team (JVET) Ad-Hoc Group on H.266/VVC Conformance and Co-editor of the H.266/VVC Conformance Testing document. Dr. Moccagatta has also been an active participant of the Alliance for Open Media (AOM) AV1 Codec WG, where she has co-authored two adopted proposals. She currently represents Intel in the AOM Board. Dr. Moccagatta is also serving as IEEE Signal Processing Society (SPS) Regional Director-at-Large Regions 1-6, supporting and advising Chapters and their officers, providing input on how to serve and engage the SPS community in general, and the SPS industry members in particular, and using her professional network to attract new volunteers to serve in SPS subcommittees and task forces. Dr. Moccagatta is the author or co-author of more than 30 publications, 2 book chapters, and more than 10 talks and tutorials in the field of image and video coding. She holds more than 10 patents in the same fields. For more details see Dr. Moccagatta professional site at http://alfiole.users.sonic.net/iole/. Dr. Moccagatta received a Diploma of Electronic Engineering from the University of Pavia, Italy, and a PhD from the Swiss Federal Institute of Technology in Lausanne, Switzerland.

Formação de RH e Projetos de PD&I no Brasil: Perspectivas para a Microeletrônica
Organizador: Marcelo Lubaszewski, UFRGS
Moderadora: Linnyer Beatrys Ruiz Aylon, SBMicro
Painelistas:
Alexandre Motta, COAPD – CNPq
Valeria Arruda, Engenharias IV – CAPES
Carlos Eduardo Pereira, Embrapii

ABSTRACT: Given the progress achieved over the last fifty years in logic synthesis and verification, it is tempting to believe that most of the research discoveries have already been made, and the role of future researchers and engineers is just to maintain the CAD tools and occasionally make small changes, such as adding concurrency or employing machine learning to generate better scripts. Nothing could be farther from the truth. In this talk, we explore several orthogonal innovations in the fundamental research used to build synthesis tools targeting FPGAs and ASICs. These innovations include using novel data structures, leveraging synergistic optimization engines, and simultaneously exploring previously-unrelated search spaces. Most of these improvements are work-in-progress with early results demonstrating better quality and faster runtimes.

BIO: Alan graduated with M.S. from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and received his Ph.D. from Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. In 2002, Alan joined the EECS Department at University of California, Berkeley, where he is currently a full researcher. His research is in computationally efficient logic synthesis, formal verification, and machine learning.

Organizador/Moderador: Arthur Liraneto – CESAR
Painelistas:
Francisco Osman Oliveira Gomes – RFiDO Design
Wellington Oliveira – BottomUp Telemetria