Rajiv V. Joshi

T. J. Watson research center, IBM


Predictive Analytics in Machine Learning

Abstract: As semiconductor technology enters the sub-14nm era, geometry, process, voltage and temperature (PVT) variability in devices can affect the performance, functionality, and power of circuits, especially in new Artificial Intelligent (AI) accelerators. This is where predictive failure analytics is extremely critical. It can identify the failure issues related to logic and memory circuits and drive the circuits in the energy efficient area. This talk describes how key statistical techniques and new algorithms can be effectively used to analyze and build robust circuits. These algorithms can be used to analyze decoders, latches, and volatile as well as non-volatile memories. In addition, how these methodologies can be extended to “reliability prediction” and “hardware corroboration” is demonstrated. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance of sample points simulations. To avoid overfitting, a cross-validation based regularization framework for ordered feature selection is demonstrated. Also, techniques to generate accurate parasitic capacitance modeling along with PVT variations for sub-22nm technologies and their incorporation into a physics-based statistical analysis methodology for accurate Vmin analysis are described. In addition, extension of these techniques based on machine learning e.g KNN is highlighted. Finally, the talk summarizes important issues in this field.

Dr. Rajiv V. Joshi is a research scientist, key technical lead and member of IBM Academy of Technology at T. J. Watson research center, IBM. He received his B.Tech I.I.T (Bombay, India), M.S (M.I.T) and Dr. Eng. Sc. (Columbia University). His novel interconnects processes and structures are universally used from sub-0.5µm to 7nm. He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. He has extensively worked on novel memory designs. He commercialized these techniques. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for licensing contributions, holds over 60 invention plateaus and has over 235 US patents and over 354 including international patents. His has worked on in-memory computation, CNN, DNN accelerators and Quantum computing. He has authored and co-authored over 200 papers. He has given over 50 invited/keynote talks and given several Seminars. He is awarded prestigious IEEE Daniel Noble award for 2018. He received the Best Editor Award from IEEE TVLSI journal. He is recipient of 2015 BMM award. He is inducted into New Jersey Inventor Hall of Fame in Aug 2014 along with pioneer Nicola Tesla. He is a recipient of 2013 IEEE CAS Industrial Pioneer award and 2013 Mehboob Khan Award from Semiconductor Research Corporation. He won several best paper award from ISSCC 1992, ICCAD 2012, ISQED, VMIC. He is a member of IBM Academy of technology and a master inventor. He served as a Distinguished Lecturer for IEEE CAS and EDS society. He is currently Distinguished Lecturer for CEDA. He is IEEE, ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay. He serves in the Board of Governors for IEEE CAS. He serves as an Associate Editor of TVLSI and ad-hoc industrial committee for Proceedings of IEEE. He has served on committees of DAC 2019, AICAS 2019, ISCAS, ISLPED (Int. Symposium Low Power Electronic Design), IEEE VLSI design, IEEE CICC, IEEE Int. SOI conference, ISQED and Advanced Metallization Program committees. He initiated IBM CAS EDS symposium at IBM in the field of Artificial Intelligence as the focal area. He successfully led AI compute symposium over 3 years. He is an industry liaison for universities as a part of the Semiconductor Research Corporation. Also, he is in the industry liaison committee for IEEE CAS society.

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