Program

Keynote Speakers

Kenneth K. O

Texas Analog Center of Excellence and Dept. of ECE,
The University of Texas at Dallas, Richardson, TX

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Rajiv V. Joshi

T. J. Watson research center, IBM

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Mohammad Al Faruque

University of California Irvine (UCI)

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Chip in the Fields Highlights

Monday
(Aug 24th) 		Tuesday
(Aug 25th) 		Wednesday
(Aug 26th)		 Thursday
(Aug 27th)		 Friday
(Aug 28th)
9h
SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
CMOS device-circuit and memory reliability.
Dr. Souvik Mahapatra,
Department of Electrical Engineering, IIT Bombay, India;
10h15
SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
Trends and challenges in nanoelectronics for
the next decade.
Dr. Elena Gnani,
Department of Electrical Electronic and Information
Engineering Guglielmo Marconi, Uni of Bologna, Italy;
11h15
SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
Recent advances in organic solar cells.
Dr Lluís Marsal.
Department of Electronic, Electric and Automatic
Engineering,Universitar Rovira i Virgili, Spain;		 8h30
Opening
8h50-9h50
Keynote 1
Predictive Analytics
in Machine Learning
Rajiv Joshi
Chair: Sergio Bampi		 8h50-9h50
Keynote 2
Opening Terahertz for Everyday
Applications
Kenneth O
Chair: Wilhelmus van Noije		 8h50-9h50
Invited
Keysight 2
Design Challenges of
mmWave Beamforming
Systems for 5G and
6G Communications
Ian Rippke
Chair: Eduardo Lima
13h30-16h
Keysight Short Course
RF Amplifier Design
and Verification using
Keysight’s PathWave
Design Solutions
Anurag Bhargava &
Andy Howard
Chair: Eduardo Lima
16h-18h
SBMicro
Assembly		 14h
SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
Design and fabrication of Sic power devices
and insertion in power electronics systems.
Dr. Victor Veliadis, Executive Director and
CTO, PowerAmerica and Professor of Electrical
and Computer Engineering,
North Carolina State University, USA;
15h15
SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
Flexible electronics.
Dr. Ioannis (John) Kymissis,
Department of Electrical Engineering,
Columbia University SEAS, USA;
17h-18h
CNPq CA-ME Meeting
Alexandre Motta, João A. Martino, Linnyer Ruiz,
Jose Camargo, Fernanda Kastensmidt.		 15h30-16h50
Invited
Keysight 1
Evaluate Electrical Performance in
Electrical-Optical
-Electrical (E-O-E)
Link Systems
HeeSoo Lee
Chair: Roberto Panepucci		 14h-15h30
Business Forum
"Semicondutores Pós Covid-19:
oportunidades para o Brasil".
Besaliel Botelho
(Presidente da Bosh da América Latina)
Rogério Nunes
(Presidente da ABISEMI)
José Gustavo Sampaio Gontijo
(Diretor do Depto. de Ciência, Tecnologia
e Inovação Digital, do MCTIC)
17h-18h30
Women in Microelectronics
Leda Lunardi
North Carolina State University
Linnyer B. Ruiz Aylon
SBMicro		 14h-15h
Keynote 3
Cross-Layer Security
of Embedded and
Cyber-Physical Systems
Mohammad Al Faruque
Chair: Fernando Moraes
16h30-17h15
Closure

Invited Keysight

HeeSoo Lee

Evaluate Electrical Performance in Electrical-Optical-Electrical (E-O-E) Link Systems

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Ian Rippke

Design Challenges of mmWave Beamforming Systems for 5G and 6G Communications

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Keysight Short Course

RF Amplifier Design and Verification using Keysight’s PathWave Design Solutions

Monday, 8/24/2020
13h30-16h00 Brazil Time (9h30-12h00 PDT)
Chair: Eduardo Lima
Short course details


Speaker #1
Anurag Bhargava

Speaker #2
Andy Howard

SBMicro-EDS/IEEE Mini-Colloquium

Following the tradition since several years, in the first day of Symposium on Microelectronics Technology and Devices (SBMicro) there is a Mini-colloquium supported by the Brazilian Microelectronics Society and the IEEE. Although this year the Symposium itself has been transferred to 2021 because of the COVID-19 outbreak, there will be a virtual Mini-colloquium that will be held on August 25. The Virtual Mini-colloquium is free of charge and will be held using Cisco Webex Meetings platform. However, attendees must apply for registration before till August 23 using the link below: https://forms.gle/q15ysuuJ68AtaAmE6

Tuesday (Aug 25th) - SBMicro-EDS/IEEE (Virtual) Mini-Colloquium
09h00
10h00 		CMOS device-circuit and memory reliability.
Dr. Souvik Mahapatra,
Department of Electrical Engineering,
IIT Bombay, India;
10h15
11h15 		Trends and challenges in nanoelectronics for the next decade.
Dr. Elena Gnani,
Department of Electrical, Electronic, and Information Engineering Guglielmo Marconi,
University of Bologna, Italy;
11h30
12h30 		Recent advances in organic solar cells.
Dr. Lluís Marsal,
Department of Electronic, Electric and Automatic Engineering,
Universitat Rovira i Virgili, Spain;
14h00
15h00 		Design and fabrication of SiC power devices and insertion in power electronics systems.
Dr. Victor Veliadis, Executive Director and
CTO, PowerAmerica and Professor of Electrical and Computer Engineering,
North Carolina State University, USA;
15h15
16h15 		Flexible electronics.
Dr. Ioannis (John) Kymissis,
Department of Electrical Engineering,
Columbia University SEAS, USA.
The 2020 EDS Brazil (Virtual) Mini-Colloquium is organized by the ED Student Branch at Centro Universitario FEI and ED Student Branch of Unicamp. It is supported by Centro Universitario FEI, Brazilian Microelectronics Society, the IEEE, State University of Campinas (Unicamp).

CHIP IN THE FIELDS PROGRAM

Wednesday (Aug 26th)
8h30 Opening
8h50
9h50 		Keynote 1
Rajiv Joshi
Chair: Sergio Bampi
10h00
11h20 		SBCCI 1
Hw Accel. And
Reconf Comp 		WCAS 1
Analog and RF
Circuits 1
11h30
12h50 		SBCCI 2
Approximate
Computing 		WCAS 2
Analog and RF
Circuits 2
LUNCH
14h00
15h20 		SBCCI 3
Bio-inspired
and biomedical
circuits 		SForum 1
Digital Design
15h30
16h50 		Invited
Keysight 1
HeSoo Lee
Chair: Roberto Panepucci 		SForum 2
Analog and RF
Circuits
17h00
Thursday (Aug 27th)
8h30
8h50
9h50 		Keynote 2
Kenneth O
Chair: Wilhelmus van Noije
10h00
11h20 		SBCCI 4
Many-core
Systems 		SForum 3
CAD
11h30
12h50 		SBCCI 5
System-Level
Digital Design 		SForum 4
Devices
LUNCH
14h00
15h20 		SBCCI 6
Optimization
and voltage
references 		WCAS 3
Digital
Applications 		Business
Forum
15h30
16h50 		WCAS 4
Industry
Applications
17h00
18h30 		Women in Microelectronics
Friday (Aug 28th)
8h30
8h50
9h50 		Invited
Keysight 2
Ian Rippke
Chair: Eduardo Lima
10h00
11h20 		SBCCI 7
Video Coding 		SBCCI 8
Amplifiers and
converters
11h30
12h50 		SBCCI 9
Design
Automation and
Reliability 		SForum 5
Digital Design
and Applications
LUNCH
14h00
15h00 		Keynote 3
Mohammad Al Faruque
Chair: Fernando Moraes
15h10
16h30 		WCAS 5
Digital
Architectures
16h30
17h15		 Closure

Notes:

1. SBCCI and WCAS - 20 min/paper including 5 min Q&A
2. SForum - 13 min/paper including 3 min Q&A

SBCCI

SBCCI 1 - Hardware Accelerators and Reconfigurable Architectures

Session Chair: Sérgio Bampi, UFRGS

S1_1
(p26)
 Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator
Tiago Knorst, Julio Vicenzi, Michael Jordan, Jonathan Homercher de Almeida, Guilherme Korol, Antonio Carlos Schneider Beck, and Mateus Beck Rutzig
UFSM, UFRGS
S1_2
(p70)
 A Management Technique for Concurrent Access to a Reconfigurable Accelerator
Raul Silva, Guilherme Korol, Michael Jordan, Marcelo Brandalero, Michael Huebner, Mônica Pereira, Mateus Beck Rutzig, and Antonio Carlos Schneider Beck
UFRGS, Brandenburg Technical University Cottbus (Germany), UFRN, UFSM
S1_3
(p16)
 Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore
Francisco Carlos Silva Junior, João Pedro dos Santos Patrocínio, Ivan Saraiva Silva, and Ricardo Pezzuol Jacobi
UNB, UFPI
S1_4
(p25)
 Hardware Accelerator for Shapelet Distance Computation in Time-Series Classificationn
Victor Oliveira Costa, Carlos Gabriel de Araújo Gewehr, Julio Costella Vicenzi, Everton Alceu Carara, and Leonardo Londero de Oliveira
UFSM

SBCCI 2 - Approximate Computing

Session Chair: Mônica Magalhães Pereira, UFRN

S2_1
(p73)
 A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design
Talita Borges, Leonardo Soares, and Cristina Meinhardt
FURG, IFRS, UFSC (best paper candidate - track Digital Circuits and Applications)
S2_2
(p24)
 2PSA: An Optimized and Flexible Power-Precision Scalable Adder
Roger Porto, Bruno Zatt, Nuno Roma, Luciano Agostini, and Marcelo Porto
UFPel, Universidade de Lisboa (Portugal)
S2_3
(p40)
 Analysis of single-module and cascade molecular analog circuits for approximate computing based on DNA Strand Displacement
Poliana Oliveira, Maria Fonte Boa, Renan Marks, Marcos Guterres, and Omar Vilela Neto
CEFETMG, UFMG, UFMS
S2_4
(p76)
 Energy reduction opportunities in Field-Coupled Nanocomputing Adders
João Fiche, Marco Sousa, Jeferson Chaves, Marco Ribeiro, Leandro Silva, Luiz Vieira, and Omar Vilela Neto
CEFETMG, UFMG

SBCCI 3 - Bio-inspired and Biomedical Circuits

Session Chair: Cesar Ramos Rodrigues, UFSC

S3_1
(p13)
 A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering
Fabian Souza de Andrade, Ana Isabela Araújo Cunha, Edson Pinto Santana, and Ygor Oliveira da Guarda Souza
UFBA
S3_2
(p17)
 Event-Based CMOS Image Sensor with Shared DVS Module for Pixel Area Reduction
Tiago Lopes, Victor Oliveira, Fernanda Oliveira, and José Gabriel Gomes
UFRJ
S3_3
(p28)
 The use of the analog wavelet filter to generate a sinusoidal signal and decompose the TEB signal into its cardiac and respiratory components in implantable cardiac pacemaker systems
Guilherme Leal, and Sandro Haddad
UNB
S3_4
(p38)
 A 0.55-V 0.1oC-Accuracy All-CMOS Temperature Sensor for Implanted Devices
Jader A. De Lima
UFSC

SBCCI 4 - Many-core Systems

Session Chair: Jarbas Silveira, UFC

S4_1
(p63)
 Reducing NoC Energy Consumption Exploring Asynchronous end-to-end GALS Communication
Iaçanã Weber, Leonardo Oliveira, Everton Alceu Carara, and Fernando Moraes
PUCRS, UFSM (best paper candidate - track SoC, NoC and Reconfigurable Systems)
S4_2
(p47)
 Multiple-objective Management based on a Distributed SDN Architecture for Many-cores
Marcelo Ruaro, and Fernando Moraes
PUCRS
S4_3
(p50)
 Mapping and Migration Strategies for Thermal Management in Many-Core Systems
Alzemiro Silva, André Luís del Mestre Martins, and Fernando Moraes
PUCRS, IFSUL (best paper candidate - track SoC, NoC and Reconfigurable Systems)
S4_4
(p27)
 Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism
Rafael Follmann Faccenda, Carlos Gabriel de Araújo Gewehr, Antonio Carlos Schneider Beck, and Mateus Beck Rutzig
UFSM, UFRGS

SBCCI 5 - System-Level Digital Design

Session Chair: Ney Laert Vilar Calazans, PUCRS

S5_1
(p65)
 A SystemC Profiling Framework to Improve Fixed-point Hardware Utilization
Alisson Carvalho, Rodolfo Azevedo, Henrique Rusa, and Daniel Formiga
UNICAMP, Idea!
S5_2
(p36)
 Firefly: An Open-source Rocket-based Intermittent Framework
Hiago Rocha, Guilherme Korol, Michael Jordan, Arthur Krause, Ronaldo Silveira, Caio Vieira, Philippe Navaux, Gabriel Luca Nazar, Luigi Carro, and Antonio Carlos Schneider Beck
UFRGS
S5_3
(p11)
 A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems
Alba Lopes, and Mônica Pereira
IFRN, UFRN
S5_4
(p52)
 CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC
Felipe Silva, Adahil Muniz, Jarbas Silveira and César Marcon
UFC, PUCRS (best paper candidate - track EDA/CAD, Test and Reliability)

SBCCI 6 - Optimization and Voltage References

Session Chair: Bernardo Leite, UFPR

S6_1
(p41)
 Performance Comparison of High-Speed Dual Modulus Prescalers using Metaheuristics Sizing/Optimization
João Navarro, and Maximiliam Luppe
USP-SC
S6_2
(p53)
 Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement
Alessandro Girardi, and Helmut Graeb
UNIPAMPA, Technical University of Munich (best paper candidate - track Analog, RF, Mixed Signal Circuits and Applications)
S6_3
(p68)
 A 37 nW MOSFET-Only Voltage Reference in 0.13 um CMOS
Vanessa Furtado de Lima, and Hamilton Klimach
UFRGS (best paper candidate - track Analog, RF, Mixed Signal Circuits and Applications)
S6_4
(p78)
 Performance and Variability Trade-offs of CMOS PTAT Generator Topologies for Voltage Reference Applications
Vanessa Furtado de Lima, Rodrigo Ataide, Sergio Bampi, and Hamilton Klimach
UFRGS

SBCCI 7 - Video Coding

Session Chair: Nuno Roma, INESC, Portugal

S7_1
(p55)
 Evaluation of Cache-Based Memory Hierarchy for Video Decoding Applications
Garrenlus Souza, Arthur Cerveira, Bruno Zatt, Sergio Bampi, and Felipe Sampaio
UFRGS, UFPel, IFSUL
S7_2
(p57)
 Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding
Luiz Neto, Marcel Corrêa, Daniel Palomino, Luciano Agostini, and Guilherme Corrêa
UFPel (best paper candidate - track Digital Circuits and Applications)
S7_3
(p71)
 A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change
Vinicius Borges, Murilo Perleberg, Vladimir Afonso, Marcelo Schiavon Porto, and Luciano Agostini
UFPel, IFSUL
S7_4
(p83)
 Standalone Rate-Distortion FME Architecture
Vanio Rodrigues Filho, Marcio Monteiro, Ismael Seidel, Mateus Grellert, and Jose Luis Guntzel
UFSC

SBCCI 8 - Amplifiers and Converters

Session Chair: François Rivet, IMS Bordeaux, France

S8_1
(p44)
 Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier
Bruno Canal, Hamilton Klimach, Sergio Bampi, and Tiago Balen
IFRS, UFRGS
S8_2
(p56)
 A Novel Multimode Single Propagation Path PA
Favero Santos, Bernardo Leite, and André Mariano
UFPR
S8_3
(p59)
 Fractional-Order Instrumentation Amplifier Transfer Function for Control Applications
Vassilis Alimisis, Georgios Pappas, and Paul Sotiriadis
Technical University of Athens (Greece)
S8_4
(p62)
 A Novel Fully Integrated ULV SC DC-DC Converter for Indoor Light Energy Harvesting
Luiz Antônio da Silva Jr., Alessandro Girardi, and Lucas Compassi Severo
UNIPAMPA

SBCCI 9 - Design Automation and Reliability

Session Chair: Omar Paranaiba Vilela Neto, UFMG

S9_1
(p80)
 A Straightforward Methodology for QCA Circuits Design
Julio Domingues, Leomar Rosa Jr, and Felipe Marques
UNIPAMPA, UFPel (best paper candidate - track EDA/CAD, Test and Reliability)
S9_2
(p58)
 Evidence of a Dynamic Fault Model in the DICE Radiation-hardened Cell
William Souza da Cruz, Jean-Max Dutertre, Jean-Baptiste Rigaud, and Guillaume Hubert
École des Mines de Saint-Étienne (France), ONERA (France)
S9_3
(p39)
 Characterization of Enclosed Layout Transistors for Analog Applications on a 130nm Technology
Gustavo Paz Platcheck, Guilherme Schwanke Cardoso, and Tiago Balen
UFRGS, IFSul
S9_4
(p21)
 Synthesis and Optimization of Majority Expressions through a Mathematical Model
Evandro Ferraz, José Virgílio de Oliveira Júnior, Alexandre C. R. da Silva, and Ian Grout
UNESP, University of Limerick (Ireland)

Brazilian Universities and Research Centers

CEFETMG - Centro Federal de Educação Tecnológica de Minas Gerais
FURG - Universidade Federal do Rio Grande
Idea! - Idea! Electronic Systems
IFRN - Instituto Federal do Rio Grande do Norte
IFRS - Instituto Federal de Tecnologia do Rio Grande do Sul
IFSUL - Instituto Federal de Educação, Ciência e Tecnologia do Rio Grande do Sul
PUCRS - Pontifícia Universidade Católica do Rio Grande do Sul
UFBA - Universidade Federal da Bahia
UFC - Universidade Federal do Ceará
UFMG - Universidade Federal de Minas Gerais
UFMS - Universidade Federal de Mato Grosso do Sul
UFPel - Universidade Federal de Pelotas
UFPI - Universidade Federal do Piauí
UFPR - Universidade Federal do Paraná
UFRGS - Universidade Federal do Rio Grande do Sul
UFRJ - Universidade Federal do Rio de Janeiro
UFRN - Universidade Federal do Rio Grande do Norte
UFSC - Universidade Federal de Santa Catarina
UFSM - Universidade Federal de Santa Maria
UNB - Universidade de Brasília
UNESP - Universidade Estadual Paulista
UNICAMP - Universidade Estadual de Campinas
UNIPAMPA - Universidade Federal do Pampa
USP-SC - Universidade de São Paulo, Escola de Engenharia de São Carlos

WCAS

WCAS 1- Analog and RF Circuits 1

Session Chair: Pietro Maris Ferreira (CentraleSupélec)

W1_1
(p14)
 A Low Power, 1.2 V, 915 MHz LNA with Cross-Coupled Capacitive Feedback and Programmable Input Impedance
Julian Herrera and Eduardo Lima
Eldorado Research Institute
W1_2
(p15)
 Multimode Differential Power Amplifier with variable output power and low gain variation for 2.45 GHz operation
Bruno Tarui and Bernardo Leite
UFPR
W1_2
(p13)
 Design and robustness assessment of a 0.8-5.2 GHz double-balanced active mixer with CMFB
Phillipe Menezes, Cláudio Dias, Eduardo Lima and Luiz Carlos Kretly
UNICAMP, Eldorado Research Institute
W1_3
(p10)
 A Low Voltage Power Converter Using a Microtransformer in MCM Technology
Antonio Telles, Marinalva Rocha, Jair Emeri, Ricardo Teixeira and Saulo Finco
CTI Renato Archer

WCAS 2- Analog and RF Circuits II

Session Chair: Pedro Emiliano Paro Filho (IQ Analog Corporation)

W2_1
(p4)
 Second-Order ΣΔ Modulator Using Amplifiers with Gain Enhancement Techniques for Low-Voltage Applications
Mateus Castro, Agord Júnior, Raphael Souza, Eduardo Lima and Leandro Manera
UNICAMP, Eldorado Research Institute
W2_2
(p20)
 System-level Design of an ULP ADPLL-based Frequency Synthesizer for IEEE 802.11ah
Bárbara Souza, Lesley Ferreira, Mateus Moreira, Filipe Baumgratz, Sandro Ferreira and Sergio Bampi
UFRGS, UNISINOS
W2_3
(p18)
 All-digital RF pulsed transmitter in FPGA with hardware complexity reduction techniques
Nágila Menezes, Hugo Hernandez, Dionísio Carvalho and Wilhelmus Van Noije
USP, UFMG (best paper candidate – Academic track)
W2_4
(p11)
 Model and simulation of Warpage in packaged IC strips after Mold Array Process
Jose Luis Ramirez, Ricardo Yoshioka, Claudemir Coral, Carolina Nunes and Igor Namba
Eldorado Research Institute (best paper candidate – Industrial track)

WCAS 3- Digital Applications

Session Chair: Yumi Monma (Cadence Design Systems)

W3_1
(p2)
 Design and Verification of a Parameterizable Interleaver and Deinterleaver for Visible Light Communication
Mateus G. Silva, Gabriel R. T. Araújo, Elisa S. Bacelar and Ricardo de Oliveira Duarte
UFMG
W3_2
(p12)
 A Synthesizable Low Complexity LDPC Encoder
Hamilton Luis, Eduardo Lima, Cassio Rodrigues, Fabio Pereira and Daniel Urdaneta
Eldorado Research Institute
W3_3
(p7)
 Exact Two-Level Disjoint Logic Minimization Based on Implicants Classes
Duarte Oliveira, Vitor Torres, Gracieth Batista and Gabriel Duarte
ITA
W3_4
(p8)
 Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools
Duarte Oliveira, Gabriel Duarte, Nicolly Cardoso and Gracieth Batista
ITA (best paper candidate – Academic track)

WCAS 4- Industry Applications

Session Chair: José Arnaldo Bianco (Cirrus Logic)

W4_1
(p25)
 A Front End Digital Design Tool for structured ASICs
Alcides Silveira Costa, Leonardo Droves, Marcos Hervé, Daniel Ferrão and André Reis
inPlace, UFRGS, CHIPUS
Invited 1
 Industry Invited Paper 1
NXP
Invited 2
 Industry Invited Paper 2
HT-Micron
Invited 3
 Industry Invited Paper 3
CEITEC

WCAS 5- Digital Architectures

Session Chair: Fernando Idalírio (Eldorado)

W5_1
(p5)
 A High-Speed Asynchronous Pipeline Architecture of SVM Classifier for ASR Application
Gracieth Batista, Duarte Oliveira and Osamu Saotome
ITA (best paper candidate – Industrial track)
W5_2
(p16)
 Design of a RISC-V Dual-core Lockstep for Fault-tolerant Systems
Rafael Viana, Marcio Silva and Jorge Barbosa
UNISINOS
W5_3
(p6)
 Synthesizing Synchronous Specifications as Quasi Delay Insensitive Asynchronous State Machines
Duarte Oliveira, Orlando Verducci, Gracieth Batista and Gabriel Duarte
ITA (best paper candidate – Academic track)
W5_4
(p24)
 A Hardware Accelerator for the Segmentation of Hyperspectral Images
Arthur Passos, Felipe Viel and Cesar Zeferino
UNIVALI (best paper candidate – Academic track)

Brazilian Universities, Research Centers and Companies

CEITEC – CEITEC S. A.
Chipus – Chipus Microelectronics S. A.
CTI Renato Archer – Renato Archer Research Center
Eldorado – Eldorado Research Institute
HT–Micron – HT Micron Semiconductores S. A.
InPlace – inPlace Design Automation
ITA – Instituto Tecnológico de Aeronáutica
NXP – NXP Semicondutors
UFMG – Universidade Federal de Minas Gerais
UFPR – Universidade Federal do Paraná
UFRGS – Universidade Federal do Rio Grande do Sul
UNICAMP – Universidade Estadual de Campinas
UNISINOS – Universidade do Vale do Rio dos Sinos
UNIVALI – Universidade do Vale do Itajaí
USP – Universidade de São Paulo

SFORUM

SFORUM 1 - Digital Design

Session Chair: José Augusto Nacif (UFV)

SF1_1
(p34)
 TOWARDS A NONVOLATILE IMPLEMENTATION OF NEANDER, AN ACCUMULATOR BASED 8-BIT PROCESSOR
Bruna Cagliari, Paulo Butzen and Raphael Brum
UFRGS (best paper candidate)
SF1_2
(p42)
 FPGA AND VLSI IMPLEMENTATION OF A DECODING ALGORITHM BASED ON INFORMATION-SET
Jefferson Rodrigo Schuertz and Sibilla Batista da Luz França
UFPR
SF1_3
(p32)
 A COMPARISON ON DIFFERENT LAYOUT TOPOLOGIES FOR VOLATILE DYNAMIC FLIP-FLOPS’ FEEDBACK BRANCH
Klaus Holler, Raphael Martins Brum and Paulo Francisco Butzen
UFRGS
SF1_4
(p43)
 DESIGN AND ROBUSTNESS EVALUATION OF A 7NM FINFET DICE SRAM
Maria Eduarda de Melo Hang and Cristina Meinhardt
UFSC
SF1_5
(p31)
 A STUDY OF VOLATILE AND NONVOLATILE STATIC RANDOM ACCESS MEMORIES
Bruno Zimmer, Raphael Brum and Paulo Butzen
UFRGS
SF1_6
(p24)
 ROBUSTNESS ANALYSIS IN SRAM BIT CELLS
Cleiton M. Marques, Cristina Meinhardt and Paulo Butzen
FURG, UFSC, UFRGS

SFORUM 2 - Analog and RF Circuits

Session Chair: Lucas Compassi Severo (UNIPAMPA)

SF2_1
(p38)
 A GM-C FILTER BANK FOR SUPRAHARMONIC ANALYSIS APPLICATION
Mateus Xavier Ferreira, Thais M. Mendes, Leandro R. M. Silva, Estêvão C. Teixeira and Carlos A. Duque
UFJF
SF2_2
(p22)
 LINEARIZATION
Maysa Araujo, Dhessica Moura and Eduardo Lima
UFPR
SF2_3
(p23)
 CMOS POWER AMPLIFIER WITH ADAPTIVE BIASING AND A 24.5 DBM OCP1DB
Jose Carlos dos Santos, Bruno Tarui and Bernardo Leite
UFPR
SF2_4
(p52)
 DESIGN AND COMPARISON OF TWO HIGH POWER-SUPPLY REJECTION CAPACITOR-LESS LOW-DROPOUT REGULATORS USING A VOLTAGE SUBTRACTOR STAGE
Rodrigo do Nascimento Tolêdo, Wenita Silva and Rafael Marinho
UFPB
SF2_5
(p37)
 DEVELOPMENT OF ASTABLE MULTIVIBRATORS POWERED BY PHOTOVOLTAIC CELLS
Erick Bento and Antonio Telles
CTI
SF2_6
(p28)
 PERFORMANCE EVALUATION OF A SELF-BIASED CURRENT REFERENCE SOURCE USING UNIFORMLY DOPED AND HALO-IMPLANTED CHANNEL TRANSISTORS
Rodrigo Dias, Rodrigo Braga, Dean Karolak, Fernanda Silva and Paulo Silva
UNIFEI
SF2_7
(p21)
 POLAR VOLTERRA SERIES FOR MODELING OF POWER AMPLIFIER AND I/Q MODULATOR
Leonardo Nakatani Moretti, Bruna T. Marcondes, Luis Schuartz and Eduardo G. Lima
UFPR

SFORUM 3 - CAD

Session Chair: Cláudio Machado Diniz (UCPel)

SF3_1
(p46)
 A RUN-TIME HARDWARE ROUTING IMPLEMENTATION FOR CGRA OVERLAYS
Mateus Pinto da Silva, Maria Dalila Vieira, Ricardo Ferreira and José Augusto Nacif
UFV
SF3_2
(p53)
 AUTOMATIC ANALOG DESIGN PROCEDURE INCLUDING STATISTICAL ANALYSIS OF CIRCUIT PERFORMANCE
Felipe Quirino and Alessandro Girardi
UNIPAMPA (best paper candidate)
SF3_3
(p30)
 SELECTIVE HARDENING METHOD TO QUICKLY ESTIMATE THE SET OF MOST CRITICAL LOGIC GATES
Glória Claro, Marcio O. Rocha and Paulo Butzen
FURG, UFRGS
SF3_4
(p25)
 THE EFFECTS OF NET ORDERING IN GLOBAL ROUTING
Arthur Bianco, Renan Netto, Tiago Fontana, Sheiny Fabre and Jose Luis Guntzel
UFSC
SF3_5
(p45)
 USING LIBFUZZER, KLEE, AND LEGUP TO VALIDATE HARDWARE DESIGNS
Josué Campos, Maria Dalila Vieira, Michael Canesche, Ricardo Ferreira and José Augusto Nacif
UFV
SF3_6
(p47)
 EXPLORING DECISION TREE METHODS TO LEARN UNKNOWN BOOLEAN FUNCTIONS
Isac Campos, Augusto Berndt, Mateus Grellert and Cristina Meinhardt
UFSC, UFRGS

SFORUM 4 - Devices

Session Chair: Rodrigo Trevisoli Doria (FEI)

SF4_1
(p29)
 COMPARISON OF THRESHOLD VOLTAGE EXTRACTION TECHNIQUES ON GE FINFETS
Isabella Scotta and Alberto Oliveira
UTFPR
SF4_2
(p48)
 ELECTRICAL CHARACTERIZATION OF MOSFETS FROM A 180 NM CMOS TECHNOLOGY
Beatriz Hilbert and M. A. Pavanello
FEI
SF4_3
(p51)
 STUDY OF SOLAR CELLS BY USING MOSFET IMPLEMENTED WITH THE OCTO LAYOUT STYLE
José Anderson Nascimento Neto and Salvador Gimenez
FEI
SF4_4
(p49)
 STUDY OF SOLAR CELLS BY USING MOSFET IMPLEMENTED WITH THE DIAMOND LAYOUT STYLE
Rafael Rivas Valdivia and Salvador Gimenez
FEI
SF4_5
(p35)
 ZERO TEMPERATURE COEFFICIENT BEHAVIOR FOR DIAMOND MOSFET
José Luiz Azevedo Jorge, Ricardo Alves Jr, Luciano Camillo, Marco Peixoto, Marcello Correa and Salvador Gimenez
CEFET-RJ, FEI
SF4_6
(p33)
 THE INFLUENCE OF THE PROTON IRRADIATION ON NFINFET INVERTER.
Gustavo de Araujo and Paula Agopian
UNESP

SFORUM 5 - Digital Design and Applications

Session Chair: Cristina Meinhardt (UFSC)

SF5_1
(p40)
 DEVELOPMENT OF A 16-QAM MODULATOR AND DEMODULATOR PYTHON MODEL SUITABLE FOR VHDL IMPLEMENTATION
Arthur Morbach, Jonas Dandanel and Sandro Ferreira
UNISINOS
SF5_2
(p20)
 MONITOR WATER: A MONITORING SYSTEM USING NODEMCU ESP8266
Tatiane Santos, Ricardo Sampaio, Vitor Bremgartner da Frota and Álvaro Peres Neto
IFAM
SF5_3
(p36)
 SUPERVISION OF PHYSICAL, CHEMICAL AND ELECTRIC VARIABLES IN MILK REFRIGERATION
Vitoria Santana, Wesley Silva, Manoel Cordeiro Neto and Geronimo Alexandre
IFPE
SF5_4
(p39)
 P4VBOX: ENABLING P4-BASED SWITCH VIRTUALIZATION
Pablo Rodrigues, Mateus Saquetti, Guilherme Bueno, Weverton Cordeiro and Jose Rodrigo Azambuja
UFRGS (best paper candidate)
SF5_5
(p44)
 NANOSCL: A STANDARD CELL LIBRARY FOR NANOMAGNETIC LOGIC
Leandro Lázaro Vieira, Larissa Isabelle Silva, Ruan Evangelista Formigoni, Michael Canesch, Ricardo Santos Ferreira and José Augusto Nacif
UFV (best paper candidate)
SF5_6
(p26)
 TEMPLATE MATCHING-BASED EYE TRACKING TECHNIQUE WITH FPGA FOR FOVEATED RENDERING
Gabriel Ayres de Oliveira and Estêvão C. Teixeira
UFJF

Brazilian Universities, Research Centers and Companies

CEFET-RJ - Centro Federal de Educação Tecnológica do Rio de Janeiro
CTI Renato Archer – Renato Archer Research Center
FEI - Centro Universitário da FEI
FURG - Universidade Federal do Rio Grande
IFAM - Instituto Federal do Amazonas
IFPB - Instituto Federal da Paraíba
UFJF - Universidade Federal de Juiz de Fora
UFPB - Universidade Federal da Paraíba
UFPR – Universidade Federal do Paraná
UFSC - Universidade Federal de Santa Catarina
UFRGS - Universidade Federal do Rio Grande do Sul
UFV - Universidade Federal de Viçosa
UNESP - Universidade do Estado de São Paulo
UNIFEI - Universidade Federal de Itajubá
UNIPAMPA - Universidade Federal do Pampa
UNISINOS – Universidade do Vale do Rio dos Sinos
UTFPR - Universidade Tecnológica Federal do Paraná

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