Intel Creates 2nd 65nm Manufacturing Process

To allow production of very low-power chips for mobile platforms and small-form factor devices, chip giant Intel Corp. said today it is developing a second 65nm process technology – this one an ultra-low power derivative of its high-performance 65nm logic manufacturing process.

Complementing its high-performance, higher power 65nm P1264 process, the P1265 process provides the ability to significantly reduce three main sources of transistor leakage in mobile devices where battery life is of the most concern, Intel technical analyst Rob Willoner told Electronic News.

Intel notes that its high-performance 65nm process represents best performance option, while the ultra-low power P1265 process is the best option for power sensitive platforms.

The process is meant to provide both power consumption and performance benefits over Intel’s current 90nm manufacturing process, and give chip designers additional options in delivering the circuit density, performance and power consumption required by users of battery-operated devices, the Santa Clara, Calif.-based company reported.

One of the factors in decreasing chip power consumption – important to mobile and battery-operated devices – is improving the design of the transistor. Lost electricity leaking from these microscopic transistors, even when they are in their ’off’ state, is a problem that is a challenge for the entire industry, Intel said.

“With the number of transistors on some chips exceeding one billion, it is clear that improvements made for individual transistors can multiply into huge benefits for the entire device,“ said Mark Bohr, senior fellow and director of Intel Process Architecture and Integration in a statement.

Intel said its 65nm processes combine higher-performance and lower-power transistors, a second-generation version of Intel's strained silicon, eight high-speed copper interconnect layers and a low-k dielectric material. Building chips using the 65nm processes will allow Intel to double the number of transistors it can build on a single chip today using Intel's 90nm technology.

The P1265 processes will manufacture transistors measuring 35nm in gate length, which will be the smallest and highest performing CMOS transistors in high-volume production. By comparison, the most advanced transistors in production today, found in Intel Pentium 4 processors, measure 50nm. Small, fast transistors are the building blocks for very fast processors.

A second-generation version of Intel’s high-performance strained silicon has also been incorporated into these 65nm processes to allow higher drive current, and increase the speed of the transistors with only a two percent increase in manufacturing cost.

Willoner also explained there is a tradeoff between performance and power dissipation, but Intel has ways of ’turning the knob’ to optimize power and performance in its manufacturing processes. “The P1265 process lets you turn the knob for much, much lower power,“ he said.

In this particular tuning process, Intel has seen transistor performance go down by half, while the power goes down many-fold.

Test chips made on Intel’s ultra-low power 65nm process technology have shown transistor leakage reduction roughly 1000 times from its standard process.

Specifically, the P1265 process technology includes transistor modifications which allow delivery of low power benefits, resulting in significant reductions in the three major sources of transistor leakage: sub-threshold leakage, junction leakage and gate oxide leakage. The benefits of reduced transistor leakage are lower power and increased battery life.

As with its 90nm process, of which there are 3 or 4 variants, Intel can be expected to do the same with these 65nm processes, Willoner said.

The P1264 65nm high-performance process is production ready. The P1265 process is expected to be ready for production in 2007.

Fonte: Eletronic News, 9/20/2005



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