24/10/2005

Fujitsu Launches 65nm Process


On the heels of Intel Corp.’s 65nm process announcement, Fujitsu Microelectronics America Inc. (FMA) reported late Tuesday the availability of its own 65nm CS200 and CS200A manufacturing processes for ASIC and COT applications aimed at SoC designs requiring high performance but low power consumption.

The CS200 series process is meant for high-end, high-performance server CPU devices and other advanced systems, while applications for the CS200A series include mobile products such as cellular phones, notebook computers, and other digital consumer products that require minimum power consumption.


The company said both processes allow gate size reductions of 25 percent compared with its 90nm technology.

Incorporating a range of transistors with different leakage-power and performance points so designers can mix transistor types to achieve both high performance and low power consumption, the CS200A technology provides an especially wide variety of transistors, ranging from low leakage for cellular phones to ultra-high speed for servers or network devices, the company noted.

A breakthrough in the 65nm technology is size, the company highlighted, with gate lengths at 30nm long, a 25 percent reduction compared with the transistor size in the Fujitsu 90nm CS100 series. The smaller transistors use a nickel polycide stack in place of the cobalt polycide/polysilicon stack used for the 90nm CS100 transistors. The lower sheet resistance of the nickel polycide ensures lower gate resistance, enabling higher speed.

Keith Horn, senior VP of sales and marketing for Fujitsu, said in a statement, the “improvements in transistor configurations and modified materials allow the 65nm CS200 transistors to exhibit superior speed and leakage characteristics. The result is a significant technological advance for our customers, reflecting Fujitsu’s continuing leadership in world-class ASIC process technology.”

Other advances in the new 65nm technology include 11 copper interconnect layers instead of 10, making it easier to implement the most complex system-on-chip designs. The minimum pitch of the metal 1 interconnect layer is only 0.18-micron, which allows a doubling of the gate wiring density compared with the 90nm CS100 series. To enhance performance and minimize power consumption further, Fujitsu uses advanced copper and porous Ultra Low-K interconnect technology, which reduces parasitic interconnect capacitance.

Fujitsu said initial tape-outs are scheduled for Q1 2006.

Packaging options include standard BGA and Flip-Chip BGA.

Fonte: Eletronic News, 9/21/2005

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