Two PhD positions are available at LIRMM laboratory, Montpellier, France, in collaboration with STMicroelectronics, Grenoble, France.
==============================
PhD Position #1 available at LIRMM / STMicroelectronics
Title: Exploring Artificial Intelligence Solutions to Characterize the Behavior of Defective Cells in Nanometer Digital Circuits
Context and Problem Statement:
Efficient and accurate library characterization is a critical step in full-chip or block-level design flows because it ensures that all library cells perform to specification under all intended operating conditions (PVT). However, traditional library characterization and validation have become increasingly expensive in terms of computation and engineering effort, due to complexity and the amount of characterized data. The traditional methodology for characterization relies on brute-force simulations. However, due to the increasing number of simulations required, characterization needs have begun to outgrow this approach. To address this problem, new solutions based on Artificial Intelligence (i.e. Machine Learning) have been proposed to accomplish fast and accurate library characterization and validation. These solutions have been implemented in characterization tools provided today by some CAD vendors.
Similarly, during the preparation of test and diagnosis flows for digital circuits, one of the main first tasks is to characterize all the cells of a given library with respect to their behavior in presence of all possible defects (open, short, resistive or not, coupling, etc.) that may affect the cell during manufacturing. This task for one cell is usually done by performing intra-cell transistor-level defect simulation using Spice to determine the output characteristics of the cell (timing information, output voltage level, etc.) and repeating this process iteratively by injecting all possible defects (one at a time) into the cell. Considering that a typical library ranges from a few hundred cells to more than a thousand, and that each cell may contain up to hundreds of defects, especially when very deep nanometer technologies are considered, the number of simulations required to fully characterize the behavior of these defective cells can be huge. Moreover, as a defect behavior depends on the operating conditions (PVT) of the circuit under investigation, a full library characterization can take a significant number of weeks (or more, depending on the number of available CAD tool licenses, memory storage capacity, etc.) and hence impact the cost of test and diagnosis.
Objectives:
The goal of this PhD thesis is to investigate the possibility to use Machine Learning techniques to accomplish fast and accurate characterization of defective cells in a given library for test and diagnosis purposes. More specifically, the main objective is to use Machine Learning techniques to build some learning models capable of predicting the full or partial characterization data of a given defective cell from the knowledge of full characterization data of other different cells in the library. Reaching this goal will avoid characterization of a full set of defective cells in a library, hence drastically reducing the overall characterization time by avoiding costly electrical (Spice) simulations. Several Machine Learning approaches and algorithms will be investigated in this study.
Keywords:
Artificial intelligence, machine learning, cell library, defective cell characterization, test, diagnosis, digital circuit
Required skills:
The applicant must have a Master or Engineering degree, with skills in the fields of computer science (especially artificial intelligence), design of digital circuits, test and diagnosis of circuits and systems. Good knowledge of programming languages (Python, Matlab, etc.) and CAD tools (Synopsys, Cadence, Mentor) is also required.
Funding and partners:
CIFRE PhD thesis done en collaboration between STMicroelectronics (Crolles) and the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM - UMR 5506 University of Montpellier / CNRS).
STMicroelectronics, 850 Rue Jean Monnet, 38920 Crolles, France http://www.st.com
LIRMM, 161 rue Ada, 34095 Montpellier, France http://www.lirmm.fr/
Starting date / duration / location:
October 2019 / 3 years / Grenoble - Montpellier
==============================
PhD Position #2 available at LIRMM / STMicroelectronics
Title: Design-for-Test and On-Line Testing of Image Sensor Matrices
Context:
The Imaging division of STMicroelectronics develops intelligent sensors for many applications. These circuits are developed for further use in emerging fields, such as future autonomous vehicles or facial recognition, in which the security of people is of primary concern. Quality, reliability and functional safety of these circuits are therefore key elements.
From a structural point of view, image sensors are made of two parts: a digital part for which test and Built-In Self-Test (BIST) techniques are well-known and established, and an analog part for which the fault coverage is essentially functional and is effective at a cost of a long test time. In addition, some applications require long and costly customized developments to integrate BIST and Built-In Self-Diagnosis (BISD) systems. However, the regularity of sensor matrices offers an area of work allowing to bring these structures closer to the digital world (such as memories for example), thus allowing the possibility to improve the test of analog parts.
Objectives:
The goal of this PhD thesis is to define generic Design-for-Test (DfT) techniques to be used in every type of product including image sensors. Constraints are numerous: optimization of the compromise between functional and structural test for analog parts, test time reduction to face the increasing complexity of circuits, integration of BIST and on-line testing techniques to ease the identification of potential failures during functioning, limited area overhead of additional embedded test structures. All of these constraints have to be considered in conjunction with a zero defect objective. In a later stage, test and diagnosis techniques developed for these image sensors will be implemented and validated on industrial circuits.
Keywords:
Test, DFT, on-line testing, system on chip, image sensor
Required skills:
The applicant must have a Master or Engineering degree, with skills in the fields of signal / image processing, design of analog / digital circuits, and test of circuits and systems. Good knowledge of programming languages (C++, Matlab, etc.) and CAD tools (Synopsys, Cadence) is also required.
Funding and partners:
CIFRE PhD thesis done en collaboration between STMicroelectronics (Grenoble) and the Laboratory of Informatics, Robotics and Microelectronics of Montpellier (LIRMM - UMR 5506 University of Montpellier / CNRS).
STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France http://www.st.com
LIRMM, 161 rue Ada, 34095 Montpellier, France http://www.lirmm.fr/
Starting date / duration / location:
October 2019 / 3 years / Grenoble - Montpellier
