Approximate computing (AxC) is a digital design technique to improve the performance and energy-efficiency requirements for many applications which inherently tolerate compute errors. Logic design for arithmetic operator approximations and timing-speculative (TS) hardware design techniques are addressed in this talk. TS hardware design paradigm allows either increasing operating frequency or decreasing the voltage beyond the limits determined by static timing analysis (STA), thereby narrowing pessimistic safety margins that conventional Digital VLSI Design methods usually adopt to prevent hardware timing errors. Timing errors need to be evaluated by accurate gate-level simulations, but a significant gap remains in practice: How do these timing errors propagate from the underlying accelerator hardware all the way up to the entire algorithm behavior, where they just may degrade the performance and quality of service of the application at stake?

  This Tutorial addresses state-of-the-art developments by the Tutorial Presenter’s group, which innovated in the design of CMOS accelerators for Machine Learning, DNN, and video and image processing.

  The tutorial has the following structure:

• Review of Approximate Adders and Approximate Multipliers;
• A cross-layer framework capable of performing investigations of AxC (i.e., from approximate arithmetic, approximate synthesis, or gate-level pruning) linking the algorithms to the VLSI logic design;
• Timing-Speculative digital VLSI hardware design (i.e., voltage over-scaling, frequency over-clocking, temperature margins, and device aging);
• Three design cases and application to illustrate AxC in practice: accelerator for image block matching, accelerator for image filtering, and AI inference engine with decision trees.

  The Approximate Computing design framework that will be presented supports the simulation of both timing and logic errors at the gate-level and the behavioral simulation of the algorithms being accelerated dynamically. In the tutorial we present a linking strategy from the VLSI hardware design with the algorithm-level behavior, and vice versa during the evolution of the application runtime. Existing frameworks perform investigations of AxC and TS techniques at circuit-level (i.e., at the output of the accelerator) agnostic to the ultimate impact at the application level (i.e., where the impact is truly manifested), leading to less optimization in the VLSI design. Unlike previous works, the approaches exposed by the presenter offer a holistic assessment of the tradeoff of AxC and TS techniques at the application-level. This framework maximizes energy efficiency and performance by identifying the maximum approximation levels at the application level to fulfill the required good enough quality.

  The tutorial, in the last part, illustrates the framework for a few design cases. We present an 8-way SAD (Sum of Absolute Differences) hardware accelerator operating in the HEVC encoder. VOS (Voltage Over-Scaling) applied to the SAD calculations.

  The Tutorial exposes and stimulates the audience to explore system-level and circuit-level design approaches for energy-efficiency, so dearly important in CMOS systems-on-chip for IoT devices.

  Target audience:

  Junior and senior undergraduate students with a basic knowledge of digital logic circuits, Graduate students in Microelectronics.

  How the intended target audience would benefit from the tutorial:

  The intended target audience will acquire an overview of current and state-of-the art techniques used in accelerators for VLSI digital design of circuits like: dedicated VLSI for deep neural networks, dedicated VLSI circuits for filters of images and videos.