Imec, Leuven, Belgium
CMOS device architecture evolution from FinFETs to nanosheet and atomic channel devices
Abstract: Recent CMOS scaling is driven by cell height scaling with reducing number of metal lines/standard cell and slow pitch scaling. For the cell height scaling with slow pitch scaling , number of fins/device must be reduced, which causes low drive current and large variability in FinFETs. Nanosheet architectures, such as nanosheet, forksheet and complementary FET (CFET), are proposed to overcome the FinFET issues. Nanosheet architectures enable wider effective transistor width and good electrostatics by stacked nanosheet channels. To scale nanosheet further, atomic channel devices by using 2D materials, such as MoS2 and WSe2, are attractive. Atomic channel devices scale contacted poly pitch beyond Si-based nanosheet devices thanks to good electrostatics by ultra-thin channel. In this presentation, we will discuss challenges and opportunities for nanosheet and atomic channel devices in CMOS scaling.
Naoto Horiguchi is the director of logic CMOS device program in imec, Leuven, Belgium. He started his carrier in semiconductor device R&D in Fujitsu Laboratories Ltd. in 1992. In 1992-1999, he was engaged in device R&D by using semiconductor nano structures in Fujitsu laboratories Ltd. and University of California, Santa Barbara. In 2000-2006, he was engaged in 90-45nm CMOS technology development in Fujitsu Ltd. From 2006, he is with imec, Leuven, Belgium, where he is engaged in advanced CMOS device R&D together with worldwide industrial partners, universities, and research institutes. His current focus is CMOS device scaling for 2nm technology node and beyond. He has co-authored numerous research papers and holds several international patents.