SBCCI 2021 Approved Papers

34ᵗʰ Symposium on Integrated Circuits and Systems Design

̶C̶a̶m̶p̶i̶n̶a̶s̶,̶ ̶S̶P̶,̶ ̶B̶r̶a̶z̶i̶l̶ ̶
Virtual
August 23 to 27, 2021


Important Dates

Camera Ready Deadline:
TBD

PaperID_1
A Latching Current Limiter with Telemetries for Space Application
Ronald Hassib Galvis Chacón, Agnaldo Dias, Ângela Alves dos Santos, Paula Cristiane Secheusk, Silvio Manea, José Alexandre Diniz and Saulo Finco

PaperID_2
A High PSRR Technique Based on 180 degree Phase Shift Biasing for Low Power Temperature Sensors
Arpan Jain, Abhishek Pullela, Ashfakh Ali and Zia Abbas

PaperID_4
MUTECO: A Framework for Collaborative Allocation in CPU-FPGA Multi-tenant Environments
Michael Jordan, Guilherme Korol, Mateus Beck Rutzig and Antonio Carlos Schneider Beck

PaperID_5
A 0.6V, 3.3nW , Adjustable Gaussian Circuit for Tunable Kernel Functions
Vassilis Alimisis, Marios Gourdouparis, Christos Dimas and Paul Sotiriadis

PaperID_6
Asymmetric Aging Avoidance EDA Tool
Freddy Gabbay, Avi Mendelson, Basel Salame and Majd Ganaiem

PaperID_7
0.5 V 19 nW Smart Temperature Sensor for Ultra-Low-Power CMOS Applications
Daniel Lott and Dalton Colombo

PaperID_8
Optimizing a Robust Miller OTA Implemented with Diamond MOSFETs By Using iMTGSPICE
José Roberto Banin Júnior, Rodrigo Moreto, Gabriel da Silva, Carlos Thomaz and Salvador Gimenez

PaperID_91
A 237 ppm/°C L-Band Active Inductance BasedVoltage Controlled Oscillator in SOI 0.18 µm
João Roberto Raposo de Oliveira Martins, Francisco Alves and Pietro Maris Ferreira

PaperID_93
Configurable Approximate Hardware Accelerator to Compute SATD and SAD Metrics for Low Power All Intra High Efficiency Video Coding
Victor Lima, Matheus Stigger, Leonardo Bandeira Soares, Cláudio Diniz and Sergio Bampi

PaperID_100
Modeling of Reconfigurable Σ∆ Modulator for Multi-standard Wireless Receivers in Verilog-A
Mateus Castro, Raphael Noal Souza, Agord Junior, Eduardo Lima and Leandro Manera

PaperID_101
High-Performance Real-Time 8K Processing AV1 Multi-Alphabet Arithmetic Decoder Design
Jiovana Gomes and Fábio Luís Livi Ramos

PaperID_102
Exploration of a Low-power CMOS Voltage Squarer
Victor Costa, Adilson Cardoso, Cesar Rodrigues, Andre Aita and Jefferson Marques

PaperID_103
Management Application - a New Approach to Control Many-Core Systems
Angelo Dalzotto, Leonardo Erthal, Marcelo Ruaro and Fernando Moraes

PaperID_104
Multifunctional auricular vagus nerve stimulator for closed-loop application
Babak Dabiri, Klaus Zeiner, Arnaud Nativel and Eugenijus Kaniusas

PaperID_106
Reflect3d: An Adaptive and Fault-Tolerant Routing Algorithm for Vertically-Partially-Connected 3D-NoC
Alexandre Almeida da Silva, Leonel Maia e Silva Junior, Alexandre Coelho, Jarbas Silveira and César Marcon

PaperID_107
High-throughput and low-power architectures for the AV1 Arithmetic Encoder
TULIO PEREIRA BITENCOURT, Fábio Luís Livi Ramos and Sergio Bampi

PaperID_108
Exploring Approximate Computing and Near-Threshold Operation to Design Energy-efficient Multipliers
Vinícius Zanandrea, Douglas Borges, Vagner Rosa and Cristina Meinhardt

PaperID_111
Evaluating the Performance, Energy and Area Tradeoffs of ATHENA in Superscalar Processors
Francisco Carlos Silva Junior, Ricardo Jacobi and Ivan Silva

PaperID_114
FLoPAD-GRU: A Flexible, Low Power, Accelerated DSP for Gated Recurrent Unit Neural Network
Ilayda Yaman, Allan Andersen, Lucas Ferreira and Joachim Rodrigues

PaperID_116
ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments
Tiago Knorst, Michael Jordan, Arthur Lorenzon, Mateus Beck Rutzig and Antonio Carlos Schneider Beck

PaperID_118
Injection-Locked Ring Oscillator based Phase Locked Loop For 1.6 Gbps Clock Recovery
Dorian Vert, Michel PIGNOL, Vincent LEBRE, Emmanuel MOUTAYE, Florence MALOU and Jean-Baptiste BEGUERET

PaperID_119
A Robust and Power-Efficient VLSI Power Line Interference Canceling Design
Morgana Macedo Azevedo da Rosa, Patrícia da Costa, Guilherme Paim, Eduardo da Costa, Sergio Almeida and Sergio Bampi

PaperID_121
Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization
AUGUSTO BERNDT, Mateus Grellert, Jônata Carvalho, Cristina Meinhardt, Isac Campos, Brunno Abreu and Bryan Lima

PaperID_123
Configurable Power/Quality-Aware Hardware Design for the AV1 Directional Intra Frame Prediction
Luiz Neto, Marcel Correa, Bruno Zatt, Daniel Palomino, Luciano Agostini and Guilherme Corrêa

PaperID_124
Novel Three-Input Gates for Silicon Quantum Dot
Maria Dalila Vieira, Icaro Moreira, Pedro Silva, Laysson Luz, Ricardo Ferreira, Omar Vilela Neto and José Augusto Nacif

PaperID_126
A Versatile Test Set Generation Tool for Structural Analog Circuit Testing
Lucas Zilch, Marcelo Lubaszewski and Tiago Balen

PaperID_128
Artificial Neural Network Based Automatic Modulation Classification System Applied to FPGA
Adenilson Castro, Ronny Milléo, Luis Lolis and André Mariano

PaperID_130
Improving energy efficiency by transparently sharing SIMD Execution Units in Assymetric Multicores
Caio Vieira and Antonio Carlos Schneider Beck

PaperID_133
A method to join the On-set and Off-set of an incompletely boolean function into a single BDD
Renato Peralta, João Nespolo, Paulo Butzen, Mariana Kolberg and Andre Reis

PaperID_134
Modeling wave propagation using automata cellular on Chip
Henrique de Moura and Daniel Munoz

PaperID_136
Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges
Ashiq Sakib

PaperID_140
Optimizing Partial Product Terms for a Power-Efficient Radix-4 Modified Booth Multiplier
Jean Scheunemann, Marlon Sigales, Mateus Fonseca and Eduardo Costa

PaperID_141
Exploring Constant Signal Propagation to Optimize Neural Network Circuits
AUGUSTO BERNDT, Paulo Butzen, Andre Reis and Cristina Meinhardt

PaperID_144
High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec
Daiane Freitas, Cláudio Diniz, Mateus Grellert and Guilherme Corrêa