SBCCI 2021 Table of Contents

 

	Tuesday	Wednesday	Thursday	Friday
08h40 - 10h20		Session 1 - Analog Design and Applications (5 papers)	Session 4 - Video Coding (5 papers)	Session 7 - Digital Design for Low Power – Circuits (4 papers)
10h30 - 11h50		Session 2 - Neural Networks (invited + 3 papers)	Session 5 - Many-core Systems (invited +3 papers)	Session 8 - Digital Design for Low Power – Architectures (invited + 3 papers)
13h00 - 14h00	Keynote Naoto Horiguchi	Keynote David Patterson	Keynote Rolf Drechsler	Keynote invited
14h10 - 15h30	Special Session SBCCI CECCI-CEDA	Session 3 - Analog Design for Low Power (4 papers)	Session 6 - Design Automation and Reliability (4 papers)	Session 9 - Quantum Computing and New Devices (3 papers)

 

Keynotes

David Patterson
Ten Lessons From Three Generations Shaped Google’s TPUv4i
University of California at Berkeley and Google, USA

Rolf Drechsler
Edge Verification: Ensuring Correctness under Resource Constraints
University of Bremen at Germany and Director of the Cyber-Physical Systems Group at the German Research Center for Artificial Intelligence (DFKI) in Bremen

Naoto Horiguchi
CMOS Device Architecture Evolution from FinFETs to Nanosheet and Atomic Channel Devices
Imec, Leuven, Belgium

 

Session 1 - Analog Design and Applications

Wednesday - 8h40 - 10h20

Session Chair: Dalton Colombo (UFMG)

1.1	A Latching Current Limiter with Telemetries for Space Applications Ronald Hassib Galvis Chacón, Agnaldo Vieira Dias, Ângela Alves dos Santos, Paula Cristiane Secheusk, Silvio Manea, José Alexandre Diniz and Saulo Finco CTI, INPE, UNICAMP
1.2	Injection-Locked Ring Oscillator based Phase Locked Loop For 1.6 Gbps Clock Recovery Dorian Vert, Michel PIGNOL, Vincent LEBRE, Emmanuel MOUTAYE, Florence MALOU and Jean-Baptiste Begueret University of Bordeaux, Centre National d'Etudes Spatiales (CNES), Thales Alenia Space (France)
1.3	A 237 ppm/°C L-Band Active Inductance BasedVoltage Controlled Oscillator in SOI 0.18 µm João Roberto Raposo de Oliveira Martins, Francisco Alves and Pietro Maris Ferreira Université Paris-Saclay (France)
1.4	Modeling of Reconfigurable Σ∆ Modulator for Multi-standard Wireless Receivers in Verilog-A Mateus Castro, Raphael Noal Souza, Agord Junior, Eduardo Lima and Leandro Manera UNICAMP, Instituto de Pesquisas Eldorado
1.5	Multifunctional auricular vagus nerve stimulator for closed-loop application Babak Dabiri, Klaus Zeiner, Arnaud Nativel and Eugenijus Kaniusas Institute of Electrodynamics, Microwave and Circuit Engineering (Austria)

 

Session 2 - Neural Networks

Wednesday - 10h30 - 11h50

Session Chair: Leandro Mateus Giacomini Rocha (IFRS)

	Machine Learning Models for EDA Application Youngsoo Shin KAIST - Korea Advanced Institute of Science and Technology (invited talk)
2.1	FLoPAD-GRU: A Flexible, Low Power, Accelerated DSP for Gated Recurrent Unit Neural Network Ilayda Yaman, Allan Andersen, Lucas Ferreira and Joachim Rodrigues Lund University (Sweden)
2.2	Exploring Constant Signal Propagation to Optimize Neural Network Circuits Augusto Berndt, Cristina Meinhardt, Paulo Butzen and Andre Reis UFRGS, UFSC
2.3	Artificial Neural Network Based Automatic Modulation Classification System Applied to FPGA Adenilson Castro, Ronny Milléo, Luis Lolis and André Mariano UFPR

 

Session 3 - Analog Design for Low Power

Wednesday - 14h10 - 15h30

Session Chair: Pietro Ferreira (Université Paris-Saclay)

3.1	A High PSRR Technique Based on 180 degree Phase Shift Biasing for Low Power Temperature Sensors Arpan Jain, Abhishek Pullela, Ashfakh Ali and Zia Abbas International Institute of Information Technology Hyderabad (India)
3.2	0.5 V 19 nW Smart Temperature Sensor for Ultra-Low-Power CMOS Applications Daniel Lott and Dalton Colombo UFMG
3.3	Exploration of a Low-power CMOS Voltage Squarer Victor Costa, Adilson Cardoso, Cesar Rodrigues, Andre Aita and Jefferson Marques UFSM, UFSC
3.4	A 0.6V, 3.3nW , Adjustable Gaussian Circuit for Tunable Kernel Functions Vassilis Alimisis, Marios Gourdouparis, Christos Dimas and Paul Sotiriadis National Technical University of Athens (Greece)

 

Session 4 - Video Coding

Thursday - 8h40 - 10h20

Session Chair: César Augusto Missio Marcon (PUCRS)

4.1	High-throughput and low-power architectures for the AV1 Arithmetic Encoder Tulio Pereira Bitencourt, Fábio Luís Livi Ramos and Sergio Bampi UFRGS, UNIPAMPA
4.2	High-Performance Design for the AV1 Multi-Alphabet Arithmetic Decoder Jiovana Gomes and Fábio Luís Livi Ramos UNIPAMPA
4.3	High-Throughput Sharp Interpolation Filter Hardware Architecture for the AV1 Video Codec Daiane Freitas, Cláudio Diniz, Mateus Grellert and Guilherme Corrêa UFPEL, UFSC, UFRGS
4.4	Configurable Power/Quality-Aware Hardware Design for the AV1 Directional Intra Frame Prediction Luiz Neto, Marcel Correa, Bruno Zatt, Daniel Palomino, Luciano Agostini and Guilherme Corrêa UFPEL
4.5	Configurable Approximate Hardware Accelerator to Compute SATD and SAD Metrics for Low Power All Intra High Efficiency Video Coding Victor Lima, Matheus Stigger, Leonardo Bandeira Soares, Cláudio Diniz and Sergio Bampi UCPel, UFRGS

 

Session 5 - Many-core Systems

Thursday - 10h30 - 11h50

Session Chair: Mônica Magalhães Pereira (UFRN)

	INVITED MANY-CORES
5.1	MUTECO: A Framework for Collaborative Allocation in CPU-FPGA Multi-tenant Environments Michael Jordan, Guilherme Korol, Mateus Beck Rutzig and Antonio Carlos Schneider Beck UFRGS, UFSM
5.2	Management Application - a New Approach to Control Many-Core Systems Angelo Dalzotto, Leonardo Erthal, Marcelo Ruaro and Fernando Moraes PUCRS
5.3	Reflect3d: An Adaptive and Fault-Tolerant Routing Algorithm for Vertically-Partially-Connected 3D-NoC Alexandre Almeida da Silva, Leonel Maia e Silva Junior, Alexandre Coelho, Jarbas Silveira and César Marcon UFC, PUCRS

 

Session 6 - Design Automation and Reliability

Thursday - 14h10 - 15h30

Session Chair: José Luís Güntzel (UFSC)

6.1	Accuracy and Size Trade-off of a Cartesian Genetic Programming Flow for Logic Optimization Augusto Berndt, Isac Campos, Brunno Abreu, Bryan Lima, Mateus Grellert, Jônata Carvalho and Cristina Meinhardt UFRGS, UFSC
6.2	A method to join the On-set and Off-set of an incompletely boolean function into a single BDD Renato Peralta, João Nespolo, Paulo Butzen, Mariana Kolberg and Andre Reis UFRGS
6.3	Asymmetric Aging Avoidance EDA Tool Freddy Gabbay, Avi Mendelson, Basel Salame and Majd Ganaiem Ruppin Academic Center and Technion – Israel Institute of Technology (Israel)
6.4	A Versatile Test Set Generation Tool for Structural Analog Circuit Testing Lucas Zilch, Marcelo Lubaszewski and Tiago Balen UFRGS

 

Session 7 - Digital Design for Low Power - Circuits

Friday - 9h00 - 10h20

Session Chair: Leonardo Bandeira Soares (IFRS)

7.1	Exploring Approximate Computing and Near-Threshold Operation to Design Energy-efficient Multipliers Vinícius Zanandrea, Douglas Borges, Vagner Rosa and Cristina Meinhardt UFSC, FURG
7.2	Optimizing Partial Product Terms for a Power-Efficient Radix-4 Modified Booth Multiplier Jean Scheunemann, Marlon Sigales, Mateus Fonseca and Eduardo Costa UCPel, UFPEL
7.3	A Robust and Power-Efficient VLSI Power Line Interference Canceling Design Morgana Macedo Azevedo da Rosa, Patrícia da Costa, Guilherme Paim, Eduardo da Costa, Sergio Almeida and Sergio Bampi UCPel, UFRGS
7.4	Soft Error Tolerant Quasi-Delay Insensitive Asynchronous Circuits: Advancements and Challenges Ashiq Sakib Florida Polytechnic University (USA)

 

Session 8 - Digital Design for Low Power - Architectures

Friday - 10h30 - 11h50

Session Chair: Fábio Luís Livi Ramos (UNIPAMPA)

	Application of injection locked relaxation oscillators to the design of ultra-low power sensor interfaces Franck BADETS CEA Leti, Département DCOS (invited talk)
8.1	Improving energy efficiency by transparently sharing SIMD Execution Units in Asymmetric Multicores Caio Vieira and Antonio Carlos Schneider Beck UFRGS
8.2	ETCG: Energy-Aware CPU Thread Throttling for CPU-GPU Collaborative Environments Tiago Knorst, Michael Jordan, Arthur Lorenzon, Mateus Beck Rutzig and Antonio Carlos Schneider Beck UFRGS, UNIPAMPA, UFSM
8.3	Evaluating the Performance, Energy and Area Tradeoffs of ATHENA in Superscalar Processors Francisco Carlos Silva Junior, Ricardo Jacobi and Ivan Silva UNB, UFPI

 

Session 9 - Quantum Computing and New Devices

Friday - 14h10 - 15h10

Session Chair: Omar Paranaiba Vilela Neto (UFMG)

9.1	Modeling wave propagation using automata cellular on Chip Henrique de Moura and Daniel Munoz UNB
9.2	Novel Three-Input Gates for Silicon Quantum Dot Maria Dalila Vieira, Icaro Moreira, Pedro Silva, Laysson Luz, Ricardo Ferreira, Omar Vilela Neto and José Augusto Nacif UFV, UFMG
9.3	Optimizing a Robust Miller OTA Implemented with Diamond MOSFETs By Using iMTGSPICE José Roberto Banin Júnior, Rodrigo Moreto, Gabriel da Silva, Carlos Thomaz and Salvador Gimenez FEI